Abstract: A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.

Abstract: New and useful methods and systems for providing lighting control are disclosed. For example, in an embodiment a lighting system includes one or more first solid state lights having a first aesthetic color, one or more second solid state lights having a second aesthetic color, the second aesthetic color having an appreciably longer wavelength than the first aesthetic color, and an amplitude correlation circuit configured to control a ratio of first light produced by the one or more first solid state lights to second light produced by the one or more second solid state lights as a function of a received dimming control signal.

Abstract: A resistive memory having a plurality of resistive elements, each having a resistance that changes with respect to a state of the resistive memory element. The resistive memory includes a substrate, a first memory access device formed on the substrate, a first contact formed on the first memory access device, and a first resistive memory element formed on the first contact. The first resistive memory element has a first polarity. The first memory access device provides read and write access to the state of the first resistive memory element. A second memory access device is formed on the substrate, a second contact formed on the second memory access device, and a second resistive memory element formed on the second contact. The second resistive memory element has a second polarity. The second memory access device provides read and write access to the state of the second resistive memory element.

Abstract: A read channel of a storage device. The read channel includes a data generator configured to generate a test symbol. An encoding circuit in a write path of the read channel is configured to encode the test symbol as a write signal and provide the write signal to a preamplifier circuit to be amplified by the preamplifier circuit. A decoding circuit in a read path of the read channel is configured to receive the write signal as amplified by the preamplifier circuit and decode the write signal as amplified by the preamplifier circuit to determine a received symbol corresponding to the encoded test symbol. A comparator is configured to compare the received symbol to the test symbol and output, based on the comparison of the received symbol and the test symbol, an indication of whether the preamplifier circuit is operational.

Abstract: A system including a plurality of cells connected in series in a rechargeable battery pack and a plurality of cell balancing modules. Each cell balancing module performs voltage balancing of a respective pair of cells. Each cell balancing module includes a communication module to (i) transmit, via a communication link, information about voltages of the respective pair of cells to an adjacent cell balancing module and (ii) receive, via the communication link, from the adjacent cell balancing module, information about voltages of cells corresponding to the adjacent cell balancing module. Each cell balancing module performs, based on the information received from the adjacent cell balancing module, the voltage balancing in response to a voltage difference between any of the plurality of cells being greater than or equal to a predetermined threshold instead of performing the voltage balancing based on a difference between voltages of the respective pair of cells.

Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.

Abstract: A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode.

Abstract: A system including a read module and a processor. The read module is configured to read data from a source supplying streaming data and to correct errors in a first portion of the data using a first error-correcting module. The first error-correcting module is unable to correct errors in a second portion of the data. The processor is configured to correct errors in the second portion of the data using a second error-correcting module. An error-correction scheme applied by the second error-correcting module is different from the error-correction scheme applied by the first error-correcting module.

Abstract: A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of a first bit line of the bit lines and a first word line of the word lines. The second memory cell is located at the intersection of a second bit line of the bit lines and a second word line of the word lines. The read/write module is configured to concurrently activate the first memory cell and the second memory cell to simultaneously access both the first memory cell and the second memory cell.

Abstract: An apparatus includes a first LED driver configured to control a first string of LEDs, a second LED driver configured to control a second string of LEDs, a third LED driver configured to control a third string of LEDs, and a control circuit configured to receive a control signal and to control the first, second, and third LED drivers so that the first, second, and third strings of LEDs cooperate in producing light according to the control signal and a color curve.

Abstract: A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

Abstract: Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria.

Abstract: Aspects of the disclosure provide a method for driving dimmable load. The method includes detecting a dimming characteristic in an energy source from which a load draws a first energy according to the dimming characteristic. The dimming characteristic requires a second energy in addition to the first energy to be drawn from the energy source to sustain an operation of the energy source. The method further includes biasing a switch to consume the second energy. The second energy and the first energy are drawn from the energy source to sustain the operation of the energy source.

Abstract: A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.

Abstract: Systems, methods, and other embodiments associated with a unified hybrid input/output adapter are described. According to one embodiment, an apparatus includes an Input/Output (I/O) interconnect configured to connect with a host device and to provide communications with the host device. The apparatus also includes a network adapter connected to the I/O interconnect and configured to communicate with a network storage. The apparatus includes a host adapter connected to the I/O interconnect and configured to communicate with a first storage device and a second storage device. The first storage device has a higher latency than the second storage device. The apparatus further includes a storage logic configured to control the I/O interconnect to cause storage access requests from the host device to be cached in the second storage device via the host adapter.

Abstract: A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks of data received by the first interface. A processor (i) determines error checking and correcting processing to be applied to each block of data of the blocks of data, and (ii) for each block of data, (a) transfers the block of data from the memory to a selected storage array of the storage arrays, and (b) assigns, to the selected storage array, the error checking and correcting processing to be applied to the block of data. The memory stores a map. The map indicates storage of the blocks of data among the storage arrays.