Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.

Abstract: A dynamic content addressable memory (CAM) is disclosed. The dynamic content addressable memory includes at least two pairs of bitlines coupled to opposite sides of at least two sense amplifiers in an open bitline configuration. Each bitline of each pair of bitlines is coupled to one of the at least two sense amplifiers, and a plurality of ternary dynamic content addressable memory cells are coupled to each of the at least pairs of bitlines. Each ternary dynamic content addressable memory cell is also coupled to a pair of search lines, a matchline, a word line and a discharge line, and further stores two bites of data in stacked capacitor storage cells. The bitlines on either side of the sense amlifiers are of equal length, and the pair of searchlines are arranged parallel to the bitlines.

Abstract: A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A dynamic content addressable memory (CAM) cell is disclosed which is suitable for constructing relatively high-speed and large-capacity CAM arrays, having binary and ternary storage capability. The cell comprises a pair of storage devices, comparing means and a pair of memory access devices. In a compare operation, the comparing means couples a match line to a discharge line during a mismatch between a pair of complementary search bits carried on a pair of search lines and a pair of complementary data bits stored in the memory. In a read or write operation, the pair of access devices are activated by a word line to couple the storage capacitors to a pair of bit lines. A ‘0’ or a ‘1’ data bit is stored when the two storage capacitors carry complementary charges. A ‘don't care’ state is stored when both capacitors are discharged.

Abstract: A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.

Abstract: Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal command and issues it to a selected one of the command sequencers. The command has associated therewith a desired latency value. A first group of one or more memory control steps for the given command is performed by the command front end if the desired latency value is less than a threshold latency value, or by the selected command sequencer if the desired latency value is greater than or equal to the threshold latency value. The remainder of the memory control steps required for the command are performed by the selected command sequencer. If the first control steps are to be performed by the selected command sequencer, then depending on the desired latency value, the command sequencer further may insert one or more wait states before doing so.

Abstract: A dynamic content addressable memory (CAM) cell is disclosed which is suitable for constructing relatively high-speed and large-capacity CAM arrays, having binary and ternary storage capability. The cell comprises a pair of storage devices, comparing means and a pair of memory access devices. In a compare operation, the comparing means couples a match line to a discharge line during a mismatch between a pair of complementary search bits carried on a pair of search lines and a pair of complementary data bits stored in the memory. In a read or write operation, the pair of access devices are activated by a word line to couple the storage capacitors to a pair of bit lines. A ‘0’ or a ‘1’ data bit is stored when the two storage capacitors carry complementary charges. A ‘don't care’ state is stored when both capacitors are discharged.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal command and issues it to a selected one of the command sequencers. The command has associated therewith a desired latency value. A first group of one or more memory control steps for the given command is performed by the command front end if the desired latency value is less than a threshold latency value, or by the selected command sequencer if the desired latency value is greater than or equal to the threshold latency value. The remainder of the memory control steps required for the command are performed by the selected command sequencer. If the first control steps are to be performed by the selected command sequencer, then depending on the desired latency value, the command sequencer further may insert one or more wait states before doing so.

Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense noes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.