Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: The invention relates to word line drivers found in embedded dynamic random access memories (DRAM) of application specific integrated circuits (ASICs). The invention is a method of programming the time at which the boosted voltage interval begins, and the period during which the boosted voltage is maintained. The result is the ability to apply the boosted voltage only when needed, thus minimizing the danger to the oxide integrity. The method comprises initiating an active row cycle in response to a leading edge of a row activation signal, initiating a precharge cycle in response to a trailing edge of the row activation signal, the precharge cycle comprising a broad line boost interval initiated by the falling edge of the row activation signal and having a predetermined duration controlled by a programmable delay circuit.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.

Abstract: A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: A random access memory comprising rowlines and columns crossing the rowlines, memory cells being associated with crossings of rowlines and columns; apparatus for connecting the memory cells to columns from voltage carried on the rowlines, the rowlines, columns and memory cells being arranged in more than two adjacent arrays; a column decoder providing access apparatus to columns in all the arrays; apparatus to disable the column access in any or all arrays and apparatus to enable a replacement spare column or columns using a spare column decoder in any or all of the arrays.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A DRAM charge storage structure including of a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.

Abstract: A method of transferring data into or out of plural memory cells of a dynamic random access memory (DRAM) comprised of precharging bitlines of the DRAM for a predetermined interval, addressing a first group of wordlines for a first period of time, after the first period of time, addressing a second group of wordlines for a second period of time, the first and second periods of time being contained within the predetermined interval, addressing and sensing a first group of memory cells from the first group of wordlines for an interval within the first period of time, addressing a second group of memory cells from the second group of wordlines within the second period of time, and transferring sensed bits from the first group of memory cells to the second group of memory cells while the second group of memory cells is being addressed.

Abstract: In a multi-level DRAM, one of multiple voltage levels may be stored in each memory cell. In a four-level system, each of a pair of bitlines is divided into two subbitlines which are connected to respective sense amplifiers. Dummy cells matching the storage cell are provided on each subbitline to balance the capacitances of the subbitlines. The stored voltage is dumped onto left and right subbitlines which are then isolated, and one of the voltages is then sensed to provide a sign bit. A second reference level is generated by dumping the charge associated with the sign bit over three subbitlines and the magnitude bit is sensed using that reference. The stored voltage is restored by charge sharing a sign bit charge on two bitlines with a magnitude bit charge on one bitline.

Abstract: A DRAM charge storage structure including a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.

Abstract: A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.