Abstract: The present invention relates to a magnetic memory element comprising a magnetic storage element comprised of two magnetic layers made of magnetic material, said two magnetic layers opposing each other in a parallel relationship and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, said two magnetic layers further having a magnetic anisotropy, while its magnetization vectors are magnetically coupled to at least one current line, wherein said two magnetic layers are arranged on a same side of said at least one current line, and a magnetic sensor element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to said magnetization vectors of said two magnetic layers of said magnetic storage element, said magnetic sensor element being electrically coupled to said at least one current line.

Abstract: An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area.

Abstract: A read-out circuit for a dynamic memory circuit has an interchanging circuit. The interchanging circuit can apply the bit lines that are connected to the storage capacitors to the second and third data output lines and to apply the bit lines that are not connected to the memory cells to the first and fourth data output lines. Sense amplifiers, in each case, are provided for amplifying a potential difference on a first line and a second line. A first sense amplifier is connected to the first and the second data output line. A second sense amplifier is connected to the third and the fourth data output line. A third sense amplifier is connected to the second and the third data output line.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.

Abstract: Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a first switching device and to a second bit line pair via a second switching device. First memory cells are arranged at crossover points between first word lines and one of the bit lines of the first bit line pair, and second memory cells are arranged at crossover points between second word lines and one of the bit lines of the second bit line pair. Data are written to the first and the second memory cells and subsequently read out. During the read-out of one of the first memory cells, the relevant first word line is activated and the first switching device is activated while the second switching device is closed, and during the read-out of one of the second memory cells, the relevant second word line is activated and the second switching device is activated while the first switching device being closed.

Abstract: An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract: One embodiment of the invention provides a method for providing defect information from an integrated memory chip having dynamic memory cells arranged on word lines and bit lines, wherein a word line group having a number of word lines may be replaced by a redundant word line group and wherein a bit line may be replaced by a redundant bit line to replace defective memory cells, wherein test data are written to the memory cells of the memory chip for the purpose of testing the memory cells, the written data being read out and compared with the previously written test data to generate first defect information items depending on the result of the comparison, the first defect information item indicating a defect if the written test data and the read-out data are different, the memory cells along one of the bit lines being read successively, the first defect information item in each case being generated for each of the read memory cells, the first defect information items being buffer-stored during the testing of

Abstract: The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Abstract: Method and system for testing a sense amplifier in a dynamic memory circuit. In one embodiment, the sense amplifier is connected to a first bit line pair via a first switching device and to a second bit line pair via a second switching device. First memory cells are arranged at crossover points between first word lines and one of the bit lines of the first bit line pair, and second memory cells are arranged at crossover points between second word lines and one of the bit lines of the second bit line pair. Data are written to the first and the second memory cells and subsequently read out. During the read-out of one of the first memory cells, the relevant first word line is activated and the first switching device is activated while the second switching device is closed, and during the read-out of one of the second memory cells, the relevant second word line is activated and the second switching device is activated while the first switching device being closed.

Abstract: A memory cell configuration connects two trench capacitors to a bit line through a contact bit terminal. Trench capacitors are disposed in a regular grid. Word and bit lines are disposed in a mutually perpendicular crossover structure. An active region in which a selection transistor of an adjoining trench capacitor is introduced is disposed respectively between two trench capacitors of a row. Trench capacitors of two rows are laterally offset with respect to one another. Two active regions of adjacent rows are electrically connected to one another through a connecting line. Connected active regions form a common terminal region connected to a contact bit terminal, which is connected to a bit line. Bit lines are disposed between rows of trench capacitors and parallel thereto. By reducing the contact bit terminals, capacitances of the bit lines are reduced and interference signal transmission between word line and contact bit terminals is reduced.

Abstract: An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area.

Abstract: In a semiconductor memory, during the rewriting of the signal stored in a memory cell, a displacement current is produced in the cell capacitor, which has to be supplied by an on-chip plate generator. If a very large number of cell capacitors are simultaneously subjected to charge reversal, as may be necessary in particular during power-up, then the plate generator cannot supply the required current within the predetermined time window. Therefore, the memory cells can assume undesired, incorrect values. It is proposed to precharge the memory cells to a predetermined potential during the switch-on of the operating voltage. Therefore, the displacement current is reduced overall, so that the plate generator can apply the required current for charging the memory cells. This measure prevents a change to the cell contents using simple measures.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: A circuit configuration for reading out a programmable link enables programming the programmable link in addition to reading out the programmed value into a volatile memory cell. For this purpose, address lines that are present are coupled to the input of the volatile memory cell by additional switches. Given the presence of a hit signal at the output of a combination unit, the switches are driven by a control circuit in a manner dependent on a set signal. The present circuit is particularly suitable for dynamic semiconductor memories and for mass production.

Abstract: The circuit configuration allows selective transmission of information items to a chip of a wafer during chip fabrication, and an apparatus having a needle card. During the test procedure of chips of a wafer which are tested in parallel, the problem can arise that, by way of example, an individual chip has a repairable defect or an incorrectly set voltage. Since a plurality of chips, for example memory modules, are tested simultaneously by a measuring device, it is not readily possible to transmit targeted information items to the individual chip. An external memory is thus assigned to each contact array on a needle card. In that memory, the individual information items are buffer-stored and transmitted to the individual chip. This affords the advantage that specific defective chips can be repaired in a simple manner without additional, costly control devices being necessary.

Abstract: A circuit configuration for reading out a programmable link enables programming the programmable link in addition to reading out the programmed value into a volatile memory cell. For this purpose, address lines that are present are coupled to the input of the volatile memory cell by additional switches. Given the presence of a hit signal at the output of a combination unit, the switches are driven by a control circuit in a manner dependent on a set signal. The present circuit is particularly suitable for dynamic semiconductor memories and for mass production.

Abstract: The invention relates to a dynamic memory cell which can be selected by means of a selection signal and the content of which can be read out by means of a bit line pair with a first and a second bit line, having a storage capacitor and a first and a second selection transistor, in which case, depending on the selection signal, a first terminal of the storage capacitor can be connected to the first bit line via the first selection transistor and a second terminal of the storage capacitor can be connected to the second bit line via the second selection transistor.

Abstract: Method and circuit for writing defect data to a defect address memory in a test system, the defect data indicating whether there is a defect in a memory area of a memory component to be tested, an address in the defect address memory being associated with the memory area, and the address of the defect address memory only being written to when the defect data item indicates a defect.