Abstract: The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The current measuring unit is connected to an output device in order to output the value of the measured current to an external test system via an external connection of the integrated circuit.

Abstract: A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

Abstract: In integrated semiconductor memories, the area taken up by a memory cell on a semiconductor substrate is always kept as small as possible to be able to accommodate as many memory cells as possible on the area of the substrate. According to the invention, word or bit lines are disposed as line pairs including two lines running one vertically above the other. As a result, two memory cells can be contact-connected in different substrate depths in a confined space. In each case different memory cells are connected to the upper line of a line pair than to the lower bit line of the same line pair. Semiconductor memories so formed require less substrate area per memory cell.

Abstract: A memory module and a method for fabricating the memory module are described. The memory module has a memory cell that is disposed in a vertical trench. The memory cell has a first and a second transistor connected in series and the first transistor is able to be turned on via a first word line and the second transistor is able to be turned on via a charge of a capacitor. The two transistors are connected between a voltage source and a bit line. In this way, the charge state of the capacitor is evaluated by the second transistor. If the capacitor has a positive charge, then the second transistor is turned on. If, moreover, the first word line is driven, then the first transistor is also turned on. As a consequence, the bit line is connected to the voltage source and supplied with a sufficiently strong signal for evaluation.

Abstract: A read-out circuit for a dynamic memory circuit has an interchanging circuit. The interchanging circuit can apply the bit lines that are connected to the storage capacitors to the second and third data output lines and to apply the bit lines that are not connected to the memory cells to the first and fourth data output lines. Sense amplifiers, in each case, are provided for amplifying a potential difference on a first line and a second line. A first sense amplifier is connected to the first and the second data output line. A second sense amplifier is connected to the third and the fourth data output line. A third sense amplifier is connected to the second and the third data output line.

Abstract: A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.

Abstract: To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract: A memory cell configuration connects two trench capacitors to a bit line through a contact bit terminal. Trench capacitors are disposed in a regular grid. Word and bit lines are disposed in a mutually perpendicular crossover structure. An active region in which a selection transistor of an adjoining trench capacitor is introduced is disposed respectively between two trench capacitors of a row. Trench capacitors of two rows are laterally offset with respect to one another. Two active regions of adjacent rows are electrically connected to one another through a connecting line. Connected active regions form a common terminal region connected to a contact bit terminal, which is connected to a bit line. Bit lines are disposed between rows of trench capacitors and parallel thereto. By reducing the contact bit terminals, capacitances of the bit lines are reduced and interference signal transmission between word line and contact bit terminals is reduced.

Abstract: It is possible to read out data in accordance with a read-out address from memory cells via bit lines and primary sense amplifiers. Each secondary sense amplifier is assigned a group of primary sense amplifiers. It is possible for the primary sense amplifiers of a group to be connected to one of the secondary sense amplifiers in each case via switching devices in order to apply the datum from one of the primary sense amplifiers to the assigned secondary sense amplifier via the switching device selected by the read-out address. For reading out data, a test control unit is provided to connect some of the switching devices in parallel depending on a test mode signal and depending on a read-out address, so that in each case one of the group of primary sense amplifiers is connected to the assigned secondary sense amplifiers.

Abstract: The invention relates to a memory circuit having a memory cell array. Memory cells in the memory cell array can be addressed via word lines and bit lines and can be written to via write amplifiers. Each of the write amplifiers is assigned to a plurality of bit lines. A datum can be written, in accordance with a write address, to a memory cell via the addressed bit line using the assigned write amplifier. An address decoding circuit is provided to simultaneously activate a plurality of the write amplifiers depending on a test mode signal so that the plurality of write amplifiers write the test datum present via the respectively assigned bit lines.

Abstract: A self-test circuit has an address generator unit for generating a test address for the purpose of testing a memory circuit and a control circuit that has signal inputs via which test commands can be applied and via which a memory access may be carried out. A first register is provided for storing an address difference value, in which case, as a result of a first test command, the address generator circuit increases the test address by the address difference value in the event of a subsequent memory access or, as a result of a second test command, the address generator circuit decreases the test address by the address difference value in the event of a subsequent memory access.

Abstract: An integrated memory circuit has a memory cell array and a test circuit. The test circuit generates an assessment datum, the assessment datum is dependent on a result of a comparison between a datum read from the memory cell array and a datum previously written to the memory cell array. A coding unit is coupled to the test circuit in order to code a plurality of assessment signals to form a coded test signal, a voltage signal is assigned to the plurality of test data as coded test datum.

Abstract: A memory module and a method for reading a data item from a memory module allow reduced interference signal injection into adjacent bit line pairs. A crossed bit line pair is provided, with one bit line in an adjacent bit line pair being disposed between the crossed bit lines. The second bit line in the adjacent bit line pair is formed to be adjacent to the crossed bit line pair. When a data item is being read, the crossed bit line pair is preferably amplified first, with the adjacent bit line pair being amplified only subsequently. This reduces the injection of an interference signal, originating from the crossed bit line pair, into the uncrossed bit line pair.

Abstract: A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Abstract: A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word lines that, in the case of a memory cell recognized as defective, are used instead of the word line regularly activated. The scrambler unit is connected to the repair unit and, thus, receives from the repair unit information on whether the redundant word line replacing a defective word line drives transistors of memory cells that can be connected to true bit lines or to complementary bit lines. As such, the scrambler unit can take the information as to whether a true bit line or a complementary bit line is driven through the spare word line into consideration when performing the test procedure. This provides for a more efficient performance of the test procedure. Also provided is a method for testing memory cells.

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

Abstract: A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Abstract: A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

Abstract: The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).