Abstract: An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. Furthermore, a control circuit is contained, having an output, which is connected to a control input of the respective switching device, and having an input, which is connected to a terminal for a test mode signal. The control circuit is configured in such a way that, within an access cycle, the respective switching device can be switched into a non-conducting state on account of an active state of the test mode signal. In the integrated memory, it is possible to measure the leakage behavior of a bit line during the read-out of a data signal.

Abstract: The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.

Abstract: In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the configuration chosen. It is thus possible to repair more defective addresses for a given number of redundant memory cells.

Abstract: In order to be able to determine precisely a temperature of a semiconductor chip, in particular a semiconductor memory, during active operation, a temperature-dependent diode structure of the chip is connected to four chip terminals using four-conductor connection technology. In this manner, an inexpensive and accurate measuring mechanism is provided for measuring the temperature.

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

Abstract: In a semiconductor memory, in particular in a DRAM, there is the problem that, during the rewriting of the signal stored in a memory cell, a displacement current is produced in the cell capacitor, which has to be supplied by an on-chip plate generator. If a very large number of cell capacitors are simultaneously subjected to charge reversal, as may be necessary in particular during power-up, then the plate generator cannot supply the required current within the predetermined time window. As a result, the memory cells can assume undesired, incorrect values. Therefore, it is proposed to precharge the memory cells to a predetermined potential during the switch-on of the operating voltage. What is advantageously achieved as a result is that the displacement current is reduced overall, so that the plate generator can apply the required current for charging the memory cells. This measure prevents a change to the cell contents using simple measures. Moreover, it is not necessary to amplify the plate generator.

Abstract: A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

Abstract: The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The current measuring unit is connected to an output device in order to output the value of the measured current to an external test system via an external connection of the integrated circuit.

Abstract: A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.

Abstract: In integrated semiconductor memories, the area taken up by a memory cell on a semiconductor substrate is always kept as small as possible to be able to accommodate as many memory cells as possible on the area of the substrate. According to the invention, word or bit lines are disposed as line pairs including two lines running one vertically above the other. As a result, two memory cells can be contact-connected in different substrate depths in a confined space. In each case different memory cells are connected to the upper line of a line pair than to the lower bit line of the same line pair. Semiconductor memories so formed require less substrate area per memory cell.

Abstract: A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

Abstract: An integrated memory circuit includes a memory cell addressed through a first word line and read through a first bit line. The first word line is connected to a word line control circuit for activating, based upon an address, a first word line associated with the memory cell to be read. A data item stored in the addressable memory cell is read through the first bit line using a read apparatus, in particular, a sense amplifier. A second word line is provided to connect a capacitance element to a second bit line, the second bit line being adjacent to the first bit line. The word line control circuit is adapted to connect the capacitance element to the second bit line using the second word line substantially simultaneously with activation of the first word line. A method for reading the data item is also provided.

Abstract: The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.

Abstract: In the memory module, depending on the configuration chosen, the number of redundant memory cells which is assigned to a defective address is also adapted to the configuration chosen. It is thus possible to repair more defective addresses for a given number of redundant memory cells.

Abstract: A memory module and a method for fabricating the memory module are described. The memory module has a memory cell that is disposed in a vertical trench. The memory cell has a first and a second transistor connected in series and the first transistor is able to be turned on via a first word line and the second transistor is able to be turned on via a charge of a capacitor. The two transistors are connected between a voltage source and a bit line. In this way, the charge state of the capacitor is evaluated by the second transistor. If the capacitor has a positive charge, then the second transistor is turned on. If, moreover, the first word line is driven, then the first transistor is also turned on. As a consequence, the bit line is connected to the voltage source and supplied with a sufficiently strong signal for evaluation.

Abstract: A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Abstract: The circuit configuration allows selective transmission of information items to a chip of a wafer during chip fabrication, and an apparatus having a needle card. During the test procedure of chips of a wafer which are tested in parallel, the problem can arise that, by way of example, an individual chip has a repairable defect or an incorrectly set voltage. Since a plurality of chips, for example memory modules, are tested simultaneously by a measuring device, it is not readily possible to transmit targeted information items to the individual chip. An external memory is thus assigned to each contact array on a needle card. In that memory, the individual information items are buffer-stored and transmitted to the individual chip. This affords the advantage that specific defective chips can be repaired in a simple manner without additional, costly control devices being necessary.

Abstract: An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. Furthermore, a control circuit is contained, having an output, which is connected to a control input of the respective switching device, and having an input, which is connected to a terminal for a test mode signal. The control circuit is configured in such a way that, within an access cycle, the respective switching device can be switched into a non-conducting state on account of an active state of the test mode signal. In the integrated memory, it is possible to measure the leakage behavior of a bit line during the read-out of a data signal.

Abstract: In order to be able to determine precisely a temperature of a semiconductor chip, in particular a semiconductor memory, during active operation, a temperature-dependent diode structure of the chip is connected to four chip terminals using four-conductor connection technology. In this manner, an inexpensive and accurate measuring mechanism is provided for measuring the temperature.

Abstract: The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).