Abstract: A memory circuit includes a plurality of memory cells and a tracking circuit. Each memory cell of the plurality of memory cells includes a cell transistor corresponding to a predetermined transistor configuration. The tracking circuit includes a first tracking bit line, a first tracking word line, a reference voltage node, and a first plurality of tracking cells. Each tracking cell of the first plurality of tracking cells includes a cell transistor corresponding to the predetermined transistor configuration. The cell transistors of the first plurality of tracking cells are electrically coupled in series between the first tracking bit line and the reference voltage node, and gate terminals of the cell transistors of the first plurality of tracking cells are electrically coupled with the first tracking word line.

Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

Abstract: A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.

Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Abstract: A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.

Abstract: A memory circuit includes a first active structure extending along a first direction, a second active structure extending along the first direction, a first conductive structure extending along a second direction, and a lowest via plug layer over the first conductive structure. The first active structure has a shared source portion corresponding to a source node of a first memory cell of the memory circuit and a source node of a second memory cell of the memory circuit. The second active structure has a shared source portion corresponding to a source node of a third memory cell of the memory circuit and a source node of a fourth memory cell of the memory circuit. The first conductive structure electrically connects the shared source portion of the first active structure with the shared source portion of the second active structure.

Abstract: A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Abstract: A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

Abstract: A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device.

Abstract: A memory includes a plurality of memory cells. A first line is over the plurality of memory cells. The first line in a first layout section includes a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A second line is over the plurality of memory cells. The second line in the first layout section includes the first metal layer and a third metal layer. The third metal layer is over the second metal layer The first line is electrically isolated from the second line. The first line and the second line extend in a same direction.

Abstract: A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value.

Abstract: A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage.

Abstract: A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor.

Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Abstract: A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.

Abstract: A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal.

Abstract: A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to the first line. The word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line.

Abstract: A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Abstract: A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.