Patents by Inventor Peter Hsu

Peter Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
    Patent number: 8946825
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Mode changing circuitry
    Patent number: 8947949
    Abstract: A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu
  • Voltage battery
    Patent number: 8942055
    Abstract: A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Annie-Li-Keow Lum, Kuoyuan (Peter) Hsu
  • Layout of memory cells
    Patent number: 8929154
    Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jacklyn Chang, Derek C. Tao, Yukit Tang, Kuoyuan (Peter) Hsu
  • Tracking mechanisms
    Patent number: 8913440
    Abstract: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Derek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
  • Writing to a memory cell
    Patent number: 8913421
    Abstract: In a method, various operations are performed based on a voltage line coupled with a plurality of memory cells. Storage nodes of the plurality of memory cells are caused to change to a first logical value. Another first logical value is applied to a plurality of data lines. Each data line of the plurality of data lines carries data for each memory cell of the plurality of memory cells. A control line of the plurality of memory cells is activated. A first voltage value is applied to the voltage line. The first voltage value causes the another first logical value on the plurality of data lines to be transferred to the storage nodes of the plurality of memory cells.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Allen Fan, Kuoyuan (Peter) Hsu
  • Cell circuits and layouts used in write tracking circuits and read tracking circuits
    Patent number: 8907428
    Abstract: A circuit includes a first transistor and a second transistor of a first type, a first transistor, a second transistor, a third transistor, and a fourth transistor of a second type. The first and second transistors of the first type, and the first transistor and the second transistor of the second type form a cross latch having a first node and a second node. A first terminal of the third transistor of the second type is coupled with the first node. A first terminal of the fourth transistor of the second type is coupled with the second node. At least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal sufficient to turn off the third transistor or the fourth transistor that is not directly from a power source.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jacklyn Chang, Derek C. Tao, Kuoyuan (Peter) Hsu
  • Metal-via fuse
    Patent number: 8847350
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Wei-Li Liao, Yun-Han Chen, Chen-Ming Hung
  • ELECTRICAL LINES WITH COUPLING EFFECTS
    Publication number: 20140268977
    Abstract: A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second output signal. The first output signal and the second output signal have coupling effects if the first signal and the second signal have coupling effects based on the first line and the second line. The first output signal and the second output signal do not have coupling effects if the first signal and the second signal do not have coupling effects.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing WANG, Kuoyuan (Peter) HSU
  • TRACKING CIRCUIT
    Publication number: 20140269026
    Abstract: A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. TAO, Annie-Li-Keow LUM, Kuoyuan (Peter) HSU
  • MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY
    Publication number: 20140247675
    Abstract: A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Inventors: Derek C. TAO, Bing WANG, Kuoyuan (Peter) HSU, Jacklyn Victoria CHANG, Young Suk KIM
  • Electrical fuse memory
    Patent number: 8824234
    Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
  • Dual rail memory
    Patent number: 8817568
    Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Derek C. Tao, Kuoyuan (Peter) Hsu, Dong Sik Jeong, Young Suk Kim, Young Seog Kim, Yukit Tang
  • Word line driver having a control switch
    Patent number: 8787109
    Abstract: A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Liao, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Signal tracking in write operations of memory cells
    Patent number: 8780652
    Abstract: In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu, Young Suk Kim
  • Circuit and method for generating a read signal
    Patent number: 8767498
    Abstract: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Tseng Huang, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Electrical fuse memory arrays
    Patent number: 8760955
    Abstract: A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Liao, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Multiple bitcells tracking scheme semiconductor memory array
    Patent number: 8760948
    Abstract: A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Derek C. Tao, Bing Wang, Kuoyuan (Peter) Hsu, Jacklyn Victoria Chang, Young Suk Kim
  • Memory circuits, systems, and operating methods thereof
    Patent number: 8750070
    Abstract: A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Huang, Kuoyuan (Peter) Hsu
  • VOLTAGE BATTERY
    Publication number: 20140146629
    Abstract: A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage.
    Type: Application
    Filed: February 12, 2013
    Publication date: May 29, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Annie-Li-Keow LUM, Kuoyuan (Peter) HSU