Abstract: In a method, a current value of a memory cell of a tracked circuit is determined. The memory cell is coupled with a data line. A tracking current value of a tracking memory cell of a tracking circuit is determined. The tracking memory cell is coupled with a tracking data line. A current value of a transistor of the tracking circuit is determined, based on a current value of a transistor of the tracked circuit, the current value of the memory cell, and the tracking current value of the tracking memory cell. A signal of the tracked circuit is generated based on a signal of the tracking circuit.

Abstract: A memory array includes a memory segment having at least one memory bank. The at least one memory bank includes an array of memory cells, and wherein at least two first read tracking cells are disposed in a read tracking column of the at least one memory bank. The memory array further includes a read tracking circuit coupled to the at least two first read tracking cells. Outputs of the at least two first read tracking cells are connected to a tracking bit connection line (TBCL). A tracking circuit connected to the TBCL is configured to output a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry. The memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Abstract: A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage.

Abstract: In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.

Abstract: A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.

Abstract: In a method, a current value of a memory cell of a tracked circuit is determined. The memory cell is coupled with a data line. A tracking current value of a tracking memory cell of a tracking circuit is determined. The tracking memory cell is coupled with a tracking data line. A current value of a transistor of the tracking circuit is determined, based on a current value of a transistor of the tracked circuit, the current value of the memory cell, and the tracking current value of the tracking memory cell. A signal of the tracked circuit is generated based on a signal of the tracking circuit.

Abstract: A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device.

Abstract: A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.

Abstract: A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to the first line. The word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line.

Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor.

Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.

Abstract: A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.

Abstract: A circuit includes a PMOS transistor, an NMOS transistor, and a logic level generation section comprising an input and a logic level output. The PMOS gate receives an input voltage having a voltage level determined based on an operational voltage, the PMOS drain is coupled to the NMOS drain and the input of the logic level generation section, and the PMOS source is coupled to the operational voltage. The NMOS gate receives a voltage that causes the NMOS transistor to have a first driving capability. The first driving capability of the NMOS transistor is less than that of the PMOS transistor if the input voltage has a voltage level greater than a predetermined voltage level.

Abstract: A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.

Abstract: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

Abstract: A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The global data line is configured to receive data to be written to the memory cell from outside of the memory array. The switching circuit is configured to electrically couple the global data line with the first local data line to transfer the data to be written to a memory cell of the first plurality of memory cells to the first local data line. The memory cell of the first plurality of memory cells is configured to receive data on the first local data line.

Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.

Abstract: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second transistor is turned on based on a second control signal delayed by a time delay from the first control signal. A second terminal of the first transistor is coupled with a second terminal of the second transistor. The second control signal is used to control a first input signal of a logic device. The logic device receives a second input signal inversed from the first control signal. An output signal of the logic device is used to control a first terminal of the second transistor.