Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing doped graphene sheets about the object to be shielded. The doped graphene sheets have a dopant concentration that is effective to reflect and/or absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than>1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Electromagnetic interference shielding structures and methods of shielding an object form electromagnetic radiation at frequencies greater than a megahertz generally include providing highly doped graphene sheets about the object to be shielded. The highly doped graphene sheets may have a dopant concentration greater than >1e1013 cm?2, which is effective to reflect the electromagnetic radiation or a dopant concentration of 1e1013 cm?2>n>0 cm?2, which is effective to absorb the electromagnetic radiation.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: The present invention provides a method for selectively placing carbon nanotubes on a substrate surface by using functionalized carbon nanotubes having an organic compound that is covalently bonded to such carbon nanotubes. The organic compound comprises at least two functional groups, the first of which is capable of forming covalent bonds with carbon nanotubes, and the second of which is capable of selectively bonding metal oxides. Such functionalized carbon nanotubes are contacted with a substrate surface that has at least one portion containing a metal oxide. The second functional group of the organic compound selectively bonds to the metal oxide, so as to selectively place the functionalized carbon nanotubes on the at least one portion of the substrate surface that comprises the metal oxide.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.