Patents by Inventor Ping Lee

Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085753
    Abstract: An electrochromic composition including: a first oxidizable compound; a reducible compound; an electrolyte; and a solvent, wherein the first oxidizable compound is represented by the following formula: wherein X1, and X2 are independently substituted or unsubstituted aliphatic hydrocarbon groups, or substituted or unsubstituted aromatic hydrocarbon groups, wherein the aromatic hydrocarbon groups include: wherein each Rx is independently hydrogen, a C1-C16 alkyl group, a C1-C16 alkoxy group, a C1-C16 haloalkyl group, or halogen.
    Type: Application
    Filed: February 24, 2023
    Publication date: March 14, 2024
    Inventors: Hao-Ping HUANG, Tsung-Hsien LIN, Yu-Nan LEE
  • Publication number: 20240090076
    Abstract: Methods, systems, and devices for wireless communications are described. A network entity may account for jitter in communications with a user equipment (UE) by adjusting connected mode discontinuous reception (CDRX) configuration parameters for the UE based on estimated downlink traffic arrival times. For a downlink traffic burst, the network entity may estimate a traffic arrival offset based on determining a traffic periodicity, an estimated arrival time associated with one or more packets of a traffic burst, and at least one jitter parameter. The jitter parameter may represent an uncertainty in the arrival time of the traffic burst. The network entity may select a CDRX offset value based on the estimated traffic arrival offset. The network entity may transmit (e.g., to a UE, such as an extended reality (XR) device) a message indicating the CDRX offset value, for example, as part of a CDRX configuration.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Prashanth Haridas Hande, Marcelo Schiocchet, Chih-Ping Li, Hyun Yong Lee, Yuchul Kim, Mickael Mondet, Vinay Melkote Krishnaprasad
  • Patent number: 11929273
    Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tsung-Sheng Kuo, Chih-Hung Huang, Guan-Wei Huang, Ping-Yung Yen, Hsuan Lee, Jiun-Rong Pai
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11923440
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20240073148
    Abstract: Certain aspects of the present disclosure provide a method for wireless communications by a node. The node receives a plurality of data packets belonging to a protocol data unit (PDU) set. Each of the plurality of data packets is associated with a dynamic priority. The node delivers the plurality of data packets to a lower layer, in accordance with the dynamic priority associated with each of the plurality of data packets.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Mickael MONDET, Ozcan OZTURK, Sitaramanjaneyulu KANAMARLAPUDI, Ravi AGARWAL, Mohamed Atef Abdelazim SHEHATA, Peerapol TINNAKORNSRISUPHAP, Prashanth Haridas HANDE, Chih-Ping LI, Hyun Yong LEE, Ovidiu Constantin IACOBOAIEA
  • Publication number: 20240066313
    Abstract: An electronic device includes a light emitting layer, a light conversion layer and an adjustable structure. The light emitting layer has a plurality of light emitting units for emitting light. The light conversion layer converts the wavelength of the light emitted by at least one light emitting unit to provide converted light. The adjustable structure is controlled to adjust a light penetrating area to correspond to the affected part to be treated, wherein at least one of the light and the converted light passes through the light penetrating area to irradiate the affected part.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Inventors: Jih-Ping LIN, Chun-Kai LEE, Fang-Iy WU, Cheng-Hsu CHOU
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240030358
    Abstract: A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 25, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yu-Cheng Lu, Chia-Hao Yu, Yeh-Yu Chiang
  • Publication number: 20240009702
    Abstract: A manufacturing method of a wafer level ultrasonic device includes: forming a first piezoelectric material layer, a first electrode material layer, a second piezoelectric material layer, and a second electrode material layer in sequence on a substrate; removing parts of those layers to form an ultrasonic element including a first electrode and a second electrode; forming a first protective layer on the ultrasonic element, and forming a first through hole and a second through hole exposing a part of the first electrode and a part of the second electrode; forming a first conductive layer and a second conductive layer on the first protective layer and connecting to the first electrode and the second electrode; forming a second protective layer; and connecting a base with an opening and the second protective layer in a vacuum environment to form a closed cavity.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
  • Publication number: 20240009703
    Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
  • Publication number: 20240011074
    Abstract: The invention provides systems and methods for determining patterns of modification to a genome of a subject by representing the genome using a graph, such as a directed acyclic graph (DAG) with divergent paths for regions that are potentially subject to modification, profiling segments of the genome for evidence of epigenetic modification, and aligning the profiled segments to the DAG to determine locations and patterns of the epigenetic modification within the genome.
    Type: Application
    Filed: June 5, 2023
    Publication date: January 11, 2024
    Applicant: Seven Bridges Genomics Inc.
    Inventors: Devin Locke, Wan-Ping Lee
  • Publication number: 20230402426
    Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 14, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shih-Hsorng Shen, Chih-Wei Su, Yu-Chun Huo
  • Publication number: 20230395527
    Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.
    Type: Application
    Filed: July 6, 2022
    Publication date: December 7, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Bo-An Tsai, Pin-Chieh Huang
  • Publication number: 20230356253
    Abstract: A droplet delivery device includes an ejector plate having an overall area that includes an outer area that is solid without holes and inner, active area with holes.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 9, 2023
    Applicant: Pneuma Respiratory, Inc.
    Inventors: Michael Scoggin, Jeffrey Miller, Caley Modlin, Chao-Ping Lee, Jianqiang Li
  • Patent number: 11806751
    Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 7, 2023
    Assignee: SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
  • Patent number: 11810648
    Abstract: Systems and methods for analyzing genomic information can include obtaining a sequence read including genetic information; identifying, within a graph representing a reference genome, a plurality of candidate mapping positions that relate to the genetic information, the graph comprising nodes representing genetic sequences and edges connecting pairs of nodes; determining, by means of a computer system, whether an alignment with the graph surrounding each of the plurality of candidate mapping positions is advanced or basic; and performing for each candidate mapping position, by means of the computer system, a local alignment based on whether the local alignment is advanced or basic. The advanced local alignment can include a first-local-alignment algorithm, and the basic local alignment includes a second-local-alignment algorithm. Based on the local alignments, the mapped position of the sequence read can be identified within the genome.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 7, 2023
    Assignee: Seven Bridges Genomics Inc.
    Inventors: Kaushik Ghose, Wan-Ping Lee
  • Publication number: 20230338602
    Abstract: The aroma diffusing device includes a base having an accommodation space inside, a heating member in the accommodation space having a heater unit and a power control unit, and a tray. The heater unit is electrically connected to the power control unit and exposed out of the base. The tray is mounted on the base contacting with the heater unit. The tray holds an aromatic essential oil which is heated by the heater unit under the control of the power control unit.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventor: HUAN-PING LEE
  • Patent number: 11794002
    Abstract: A neuromodulation probe includes a body and at least one coil set. The body has a first axis and a length along the first axis. The at least one coil set includes at least one coil, and the at least one coil is formed by winding spirally a conductive wire plural times about a second axis inside the body or on an outer surface of the body. The second axis is parallel to the first axis. The at least one coil has two opposite wire ends for providing an electric current to flow in or out of the at least one coil.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: October 24, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jo-Ping Lee, Chieh-Feng Chang, Chung-Hsin Su, Kun-Ta Wu, Chii-Wann Lin
  • Patent number: 11793945
    Abstract: A droplet delivery device includes a housing with a mouthpiece port or outlet from a nasal device for releasing fluid droplets, a fluid reservoir, and an ejector bracket having a membrane positioned between a mesh with a plurality of openings and a vibrating member that is coupled to an electronic transducer, such as an ultrasonic transducer. The transducer vibrates the vibrating member which causes the membrane to push fluid supplied by the reservoir through the mesh to generate droplets in an ejected stream released through the outlet.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Pneuma Respiratory, Inc.
    Inventors: Charles Eric Hunter, Michael Scoggin, Jeffrey Miller, Jose Salazar, Brian Beach, Caley Modlin, Matthew Culpepper, Jianqiang Li, Chengjie Li, Shi Bo Wang, Chao-Ping Lee, Gregory Rapp, Judson Sidney Clements