Patents by Inventor Ping Lee

Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11810648
    Abstract: Systems and methods for analyzing genomic information can include obtaining a sequence read including genetic information; identifying, within a graph representing a reference genome, a plurality of candidate mapping positions that relate to the genetic information, the graph comprising nodes representing genetic sequences and edges connecting pairs of nodes; determining, by means of a computer system, whether an alignment with the graph surrounding each of the plurality of candidate mapping positions is advanced or basic; and performing for each candidate mapping position, by means of the computer system, a local alignment based on whether the local alignment is advanced or basic. The advanced local alignment can include a first-local-alignment algorithm, and the basic local alignment includes a second-local-alignment algorithm. Based on the local alignments, the mapped position of the sequence read can be identified within the genome.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 7, 2023
    Assignee: Seven Bridges Genomics Inc.
    Inventors: Kaushik Ghose, Wan-Ping Lee
  • Publication number: 20230338602
    Abstract: The aroma diffusing device includes a base having an accommodation space inside, a heating member in the accommodation space having a heater unit and a power control unit, and a tray. The heater unit is electrically connected to the power control unit and exposed out of the base. The tray is mounted on the base contacting with the heater unit. The tray holds an aromatic essential oil which is heated by the heater unit under the control of the power control unit.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventor: HUAN-PING LEE
  • Patent number: 11794002
    Abstract: A neuromodulation probe includes a body and at least one coil set. The body has a first axis and a length along the first axis. The at least one coil set includes at least one coil, and the at least one coil is formed by winding spirally a conductive wire plural times about a second axis inside the body or on an outer surface of the body. The second axis is parallel to the first axis. The at least one coil has two opposite wire ends for providing an electric current to flow in or out of the at least one coil.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: October 24, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jo-Ping Lee, Chieh-Feng Chang, Chung-Hsin Su, Kun-Ta Wu, Chii-Wann Lin
  • Patent number: 11793945
    Abstract: A droplet delivery device includes a housing with a mouthpiece port or outlet from a nasal device for releasing fluid droplets, a fluid reservoir, and an ejector bracket having a membrane positioned between a mesh with a plurality of openings and a vibrating member that is coupled to an electronic transducer, such as an ultrasonic transducer. The transducer vibrates the vibrating member which causes the membrane to push fluid supplied by the reservoir through the mesh to generate droplets in an ejected stream released through the outlet.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Pneuma Respiratory, Inc.
    Inventors: Charles Eric Hunter, Michael Scoggin, Jeffrey Miller, Jose Salazar, Brian Beach, Caley Modlin, Matthew Culpepper, Jianqiang Li, Chengjie Li, Shi Bo Wang, Chao-Ping Lee, Gregory Rapp, Judson Sidney Clements
  • Publication number: 20230310342
    Abstract: Compositions and methods for reducing, or inhibiting bone loss in a subject in need thereof have been developed. Pharmaceutical compositions including one or more osteogenic compounds, or functional derivatives thereof, in an effective amount to reduce, or inhibit bone loss, or promote bone formation, preferably via stimulation of osteoblast differentiation, are provided. The compositions are particularly suited for treating bone loss associated with osteoporosis. Methods for treating, or preventing bone loss using the composition, optionally in combination with one or more therapeutic, prophylactic or diagnostic agents, or procedures, are described.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Applicant: GoldPorp Pharma Limited
    Inventors: Chi-Ming CHE, Lai-King SY, Chun-Nam LOK, Wai-Ping LEE
  • Publication number: 20230301751
    Abstract: A distinguishing device for dental plaque and dental calculus includes a light-emitting diode, an image sensing unit, and a processor. The light-emitting diode movies in a first direction and is separated from teeth in an oral cavity by a predetermined distance in a second direction. The second direction is perpendicular to the first direction. The light-emitting diode generates a blue light to illuminate the teeth, so that dental plaque on the teeth generates a first autofluorescence and dental calculus on the teeth generates a second autofluorescence. The image sensing unit is configured to sense the first autofluorescence and the second autofluorescence. The processor is coupled to the image sensing unit to distinguish a dental plaque area from a dental calculus area on the teeth according to the first autofluorescence and the second autofluorescence.
    Type: Application
    Filed: August 4, 2022
    Publication date: September 28, 2023
    Inventors: Kai-Ju CHENG, Yu-Hsun CHEN, Hao-Ping LEE, Tong-Ming HSU, Chin-Yuan TING, Shao-Ang CHEN, Kuan-Chung CHEN, Hsin-Lun HSIEH
  • Publication number: 20230298316
    Abstract: An image classifying device is provided in the invention. The image classifying device includes a storage device, a calculation circuit and a classifying circuit. The storage device stores information corresponding to a plurality of image classes. The calculation circuit obtains a target image from an image extracting device and obtains the feature vector of the target image. The calculation circuit obtains a first estimation result corresponding to the target image based on the information corresponding to the plurality of image classes and the feature vector and obtains a second estimation result corresponding to the target image based on a reference image, wherein the reference image corresponds to one of the image classes. The classifying circuit adds the target image into one of the image classes based on the first estimation result and the second estimation result.
    Type: Application
    Filed: June 23, 2022
    Publication date: September 21, 2023
    Inventors: Chia-Yuan CHANG, Kai-Ju CHENG, Yu-Hsun CHEN, Hao-Ping LEE, Tong-Ming HSU, Chin-Yuan TING, Shao-Ang CHEN, Kuan-Chung CHEN
  • Patent number: 11764277
    Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Fan Peng, Yuan-Ching Peng, Yu-Bey Wu, Yu-Shan Lu, Ying-Yan Chen, Yi-Cheng Li, Szu-Ping Lee
  • Patent number: 11749699
    Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.
    Type: Grant
    Filed: July 10, 2022
    Date of Patent: September 5, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Publication number: 20230272483
    Abstract: The invention provides oncogenomic methods for detecting tumors by identifying circulating tumor DNA. A patient-specific reference directed acyclic graph (DAG) represents known human genomic sequences and non-tumor DNA from the patient as well as known tumor-associated mutations. Sequence reads from cell-free plasma DNA from the patient are mapped to the patient-specific genomic reference graph. Any of the known tumor-associated mutations found in the reads and any de novo mutations found in the reads are reported as the patient’s tumor mutation burden.
    Type: Application
    Filed: November 30, 2022
    Publication date: August 31, 2023
    Applicant: Seven Bridges Genomics Inc.
    Inventors: Wan-Ping Lee, Devin Locke
  • Publication number: 20230253479
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Patent number: 11715669
    Abstract: A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: August 1, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Tse-Hsien Wu, Pin-Chieh Huang, Yu-Hsiang Chien, Yeh-Yu Chiang
  • Publication number: 20230220517
    Abstract: A nano-twinned Cu—Ni alloy layer is provided, wherein more than 50% in volume of the nano-twinned Cu—Ni alloy layer comprises plural twinned grains, the plural twinned grains comprise plural columnar twinned grains, and a Ni content in the nano-twinned Cu—Ni alloy layer is in a range from 0.05 at % to 20 at %. In addition, a method for manufacturing the aforesaid nano-twinned Cu—Ni alloy layer is also provided.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 13, 2023
    Inventors: Chih CHEN, Kang-Ping LEE, Yu-I CHANG, Yun-Hsuan CHEN
  • Patent number: 11697835
    Abstract: The invention provides systems and methods for determining patterns of modification to a genome of a subject by representing the genome using a graph, such as a directed acyclic graph (DAG) with divergent paths for regions that are potentially subject to modification, profiling segments of the genome for evidence of epigenetic modification, and aligning the profiled segments to the DAG to determine locations and patterns of the epigenetic modification within the genome.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 11, 2023
    Assignee: Seven Bridges Genomics Inc.
    Inventors: Devin Locke, Wan-Ping Lee
  • Publication number: 20230201598
    Abstract: A movement monitor sensor includes a body, a conduction area, at least one depth electrode set and a flat electrode set. The body has an axis and two axial ends. The conduction area at one axial end connects a conductive wire. The depth electrode set includes four separate depth electrodes disposed on the body by surrounding the axis and connected individually with first wires. The flat electrode set includes a substrate disposed at another axial end and four separate flat electrodes disposed at the substrate by surrounding the axis and connected individually with second wires. The conductive wire, the first and second wires are individually connected with the conduction area, the depth electrodes and the flat electrodes. When a human movement changes, a processor evaluates impedance variations generated by the depth electrode set, the flat electrode set and/or the conduction area to determine electrical stimulation control upon human brain.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 29, 2023
    Inventors: JO-PING LEE, SHENG-HONG TSENG, CHUNG-HSIN SU, YUNG-HSIANG WU
  • Publication number: 20230204627
    Abstract: A manufacturing process for electrode of neuromodulation probe includes the steps of: preparing a plurality of the manufacturing fixtures for electrode of neuromodulation probe; preparing a plurality of the manufacturing fixtures for electrode in a surrounding manner by having the first-layer frames to be externally disposed side by side with the bevels of the two neighboring first-layer frames close to each other, so that the second-layer frames, the plurality of electrodes and the plurality of wires are enclosed thereinside; placing a cylinder amid the plurality of manufacturing fixtures for electrode to have the plurality of wires to surround the cylinder; having a fluid plastic to surround the cylinder by filling all the spaces between the plurality of wires and the plurality of electrodes, and waiting the fluid plastic to cure; removing the plurality of first-layer frames and the plurality of second-layer frames; and, pulling off the cylinder.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 29, 2023
    Inventors: JO-PING LEE, KUN-TA WU, WEI-CHIN HUANG, AN-LI CHEN
  • Patent number: 11688683
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: June 27, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
  • Patent number: 11652155
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20230094400
    Abstract: A capacitor structure including a substrate, at least one first dielectric layer, at least one second dielectric layer, a capacitor, and an interconnect structure is provided. The substrate includes a capacitor region and a non-capacitor region. The first dielectric layer is located in the capacitor region and the non-capacitor region. The second dielectric layer is located in the non-capacitor region. At least a portion of the second dielectric layer is located in the first dielectric layer. A material of the second dielectric layer is different from a material of at least a portion of the first dielectric layer. A dielectric constant of the second dielectric layer is smaller than a dielectric constant of at least a portion of the first dielectric layer. The capacitor is located in the first dielectric layer in the capacitor region. The interconnect structure is located in the second dielectric layer in the non-capacitor region.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 30, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shih-Jan Tung, Sz-Chi Li
  • Publication number: 20230079629
    Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Wen-Hsien Chen