Patents by Inventor Ping Lee

Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285530
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20220282389
    Abstract: A nano-twinned copper layer with a doped metal element is disclosed, wherein the nano-twinned copper is doped with at least one metal element selected from the group consisting of Ag, Ni, Al, Au, Pt, Mg, Ti, Zn, Pd, Mn and Cd in a region from a surface of the nano-twinned copper layer to a depth being 0.3 ?m, and a content of the metal element in the region is ranged from 0.5 at % to 20 at %. In addition, at least 50% in volume of the nano-twinned copper layer includes plural twinned grains. Furthermore, a substrate including the aforesaid nano-twinned copper layer and a method for preparing the aforesaid nano-twinned copper layer are also disclosed.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 8, 2022
    Inventors: Chih CHEN, Kang-Ping LEE
  • Patent number: 11424280
    Abstract: A solid-state image sensor with pixels each including a photoelectric conversion portion made of a second type doped semiconductor layer and a semiconductor material layer, and the second type doped semiconductor layer contacts a first type doped semiconductor substrate. An anti-reflective portion is provided with multiple micro pillars on the semiconductor material layer, wherein micro pillars are isolated by recesses extending into the photoelectric conversion portion, and the refractive index of the micro pillar gradually decreases from bottom to top and is smaller than the refractive index of the light-receiving portion of the semiconductor material layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Publication number: 20220231022
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration in a range of 5% to 30%; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer to a range of 1% to 5%; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20220226862
    Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.
    Type: Application
    Filed: May 28, 2021
    Publication date: July 21, 2022
    Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
  • Publication number: 20220224081
    Abstract: A surface-emitting laser including a cladding layer, an active region, a first grating, a plurality of second gratings, a first electrode, and a second electrode is provided. The active region is disposed on the cladding layer. The first grating is disposed on the active region. The second gratings are disposed on the active region and separately distributed among the first grating. A diffraction order of the first grating is different from a diffraction order of the second gratings. The first electrode is electrically connected to the cladding layer. The second electrode covers at least the first grating.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 14, 2022
    Applicant: Phosertek Corporation
    Inventors: Chien-Ping Lee, Kuo-Jui Lin, Chien-Hung Lin, Bo-Tsun Chou
  • Patent number: 11367727
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Patent number: 11367728
    Abstract: Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 21, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Shyng-Yeuan Che, Hsiao-Pei Lin, Po-Yi Wu, Kuo-Fang Huang
  • Publication number: 20220184382
    Abstract: A neuromodulation probe includes a body and at least one coil set. The body has a first axis and a length along the first axis. The at least one coil set includes at least one coil, and the at least one coil is formed by winding spirally a conductive wire plural times about a second axis inside the body or on an outer surface of the body. The second axis is parallel to the first axis. The at least one coil has two opposite wire ends for providing an electric current to flow in or out of the at least one coil.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 16, 2022
    Inventors: JO-PING LEE, CHIEH-FENG CHANG, CHUNG-HSIN SU, KUN-TA WU, CHII-WANN LIN
  • Publication number: 20220180507
    Abstract: Disclosed in embodiments of the present application are a method and a product for AI processing of tumor based on VRDS 4D medical images, which is applied to medical imaging apparatuses, and the method includes: determining a bitmap BMP data source according to a plurality of scanned images associated with a target organ of a target user, generating target medical image data according to the BMP data source; determining abnormal data in target medical image data; determining the attribute information of a tumor of the target user according to the abnormal data; performing 4D medical imaging according to the target medical image data, and outputting the attribute information of the tumor. The embodiment of this application is facilitated to improve the accuracy and efficiency of tumor recognition.
    Type: Application
    Filed: August 16, 2019
    Publication date: June 9, 2022
    Inventors: Stewart Ping LEE, David Wei LEE
  • Publication number: 20220172823
    Abstract: A method and a product for AI processing of artery and vein based on VRDS 4D medical images, the method is applied to a medical imaging apparatus, and the method includes: the medical imaging apparatus first determines a bitmap (BMP) data source according to a plurality of scanned images of a target site of a target user, second generates target medical image data according to the BMP data source, and finally performs 4D medical imaging according to the target medical image data, wherein the target medical image data includes at least a data set of a blood vessel in the target site, and a data set of a vein is a transfer function result of a cubic space of a surface of the vein and a tissue structure inside the vein, and an intersection position of the artery and a vein presents an overall separation image effect.
    Type: Application
    Filed: August 16, 2019
    Publication date: June 2, 2022
    Inventors: Stewart Ping LEE, David Wei LEE
  • Publication number: 20220172351
    Abstract: Disclosed in the present application are a method and a product for AI processing of tumor and blood vessel based on VRDS 4D medical images, including determining a bitmap BMP data source; generating target medical image data according to the BMP data source; determining abnormal data in the target medical image data, a target tissue includes the target organ and a blood vessel; determining an association relationship between a tumor and a blood vessel of the target user according to a data set of the blood vessel and the abnormal data; performing 4D medical imaging according to the target medical image data, and outputting the association relationship between the tumor and the blood vessel, which is facilitated to improve the accuracy and efficiency of the medical imaging apparatus in recognizing the association relationship between a tumor and a blood vessel.
    Type: Application
    Filed: August 16, 2019
    Publication date: June 2, 2022
    Inventors: David Wei LEE, Stewart Ping LEE
  • Patent number: 11349014
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Patent number: 11339308
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten and titanium is provided comprising: providing the substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; a chitosan; a dicarboxylic acid, wherein the dicarboxylic acid is selected from the group consisting of propanedioic acid and 2-hydroxypropanedioic acid; a source of iron ions; a colloidal silica abrasive with a positive surface charge; and, optionally pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) and some of the titanium (Ti) is polished away from the substrate with a removal selectivity for the tungsten (W) relative to the titanium (Ti).
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 24, 2022
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Wei-Wen Tsai, Lin-Chen Ho, Cheng-Ping Lee, Jiun-Fang Wang
  • Publication number: 20220148162
    Abstract: A method and a product for AI endoscope analyzing of vein based on VRDS 4D medical images, which is applied to medical imaging apparatus, and the method includes: determining a bitmap (BMP) data source according to a plurality of scanned images of a target site of a target user, wherein the target site includes a target vein to be observed and an artery, a kidney and a hepatic portal associated with the target vein; generating first medical image data according to the BMP data source; generating second medical image data according to the first medical image data; processing the second medical image data to obtain target medical image data; extracting a data set of the target vein in the target medical image data; performing 4D medical imaging according to the data set of the target vein to display an internal image of the target vein.
    Type: Application
    Filed: August 16, 2019
    Publication date: May 12, 2022
    Inventors: Stewart Ping LEE, David Wei LEE
  • Publication number: 20220148163
    Abstract: A method and a product for AI recognizing of embolism based on VRDS 4D medical image, the method is applied to a medical imaging apparatus, and the method includes the following steps: determining a bitmap (BMP) data source according to a plurality of scanned images of a target site of a target user, wherein the target site includes an embolism formed on a wall of a target blood vessel; generating target medical image data according to the BMP data source; performing 4D medical imaging according to the target medical image data and determining a feature attribute of the embolism according to an imaging result, wherein the feature attribute includes at least one of the following: density, crawling direction, correspondence with a site of cancer focus and edge characteristics; and determining a type of the embolism according to the features and outputting the type.
    Type: Application
    Filed: August 16, 2019
    Publication date: May 12, 2022
    Inventors: David Wei LEE, Stewart Ping LEE
  • Publication number: 20220148222
    Abstract: An image three-dimensional measurement method, an electronic device, a storage medium and a program, product are disclosed, wherein the image three-dimensional measurement method includes the following steps: performing feature extraction on a medical image scanned by a scanning device; performing image matching on the extracted medical image; performing calibration on the scanning device to determine an internal parameter of the scanning device; performing three-dimensional reconstruction on the medical image according to the internal parameter of the scanning device to obtain a three-dimensional image; and projecting the three-dimensional image onto a two-dimensional image, and calculating a size of a target area according to a mapping relationship between three-dimensional spatial points and two-dimensional image points.
    Type: Application
    Filed: August 15, 2019
    Publication date: May 12, 2022
    Inventors: David Wei LEE, Stewart Ping LEE
  • Publication number: 20220139825
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hsiao-Pei Lin, Shih-Ping Lee, Cheng-Zuo Han
  • Publication number: 20220139054
    Abstract: Disclosed in embodiments of the present application are a method and a product for processing of VRDS 4D medical images, the method is applied to a medical imaging apparatus, and the method includes: performing initial data analysis processing on a plurality of scanned images to obtain an image source including image features of a target site of a target user; performing post-data processing on the image source to obtain N first image data sets; performing preset processing on the N first image data sets to obtain N second image data sets; performing VRDS 4D medical image display according to the N second image data sets. The embodiment of this application is facilitated to improve the refinement degree and accuracy of the medical imaging apparatus in performing medical image display.
    Type: Application
    Filed: August 16, 2019
    Publication date: May 5, 2022
    Inventors: Stewart Ping LEE, David Wei LEE
  • Publication number: 20220137909
    Abstract: A method and a product for multi-device AI linkage displaying of a VRDS 4D medical image, the method includes: extracting first partial image data from a target 4D image data according to preset raw spatial attitude information and display screen parameters of a first display device, and extracting second partial image data from the target 4D image data according to the raw spatial attitude information and display screen parameters of a second display device; and displaying the first partial image data on the first display device and displaying the second partial image data on the second display device; judging whether to enable a linkage display function when receiving first spatial attitude information and second spatial attitude information; if so, selecting the spatial attitude information of a display device with high display priority as reference spatial attitude information; adjusting image data displayed by a display device with low display priority.
    Type: Application
    Filed: August 16, 2019
    Publication date: May 5, 2022
    Inventors: David Wei LEE, Stewart Ping LEE