Patents by Inventor Ping Lee

Ping Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11590536
    Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: February 28, 2023
    Assignees: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL, SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.
    Inventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
  • Publication number: 20230035349
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11569121
    Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: I-Ping Lee, Kwang-Ming Lin, Chih-Cherng Liao, Ya-Huei Kuo, Pei-Yu Chang, Ya-Ting Chang, Tsung-Hsiung Lee, Zheng-Xian Wu, Kai-Chuan Kan, Yu-Jui Chang, Yow-Shiuan Liu
  • Patent number: 11560639
    Abstract: A nano-twinned copper layer with a doped metal element is disclosed, wherein the nano-twinned copper is doped with at least one metal element selected from the group consisting of Ag, Ni, Al, Au, Pt, Mg, Ti, Zn, Pd, Mn and Cd in a region from a surface of the nano-twinned copper layer to a depth being 0.3 ?m, and a content of the metal element in the region is ranged from 0.5 at % to 20 at %. In addition, at least 50% in volume of the nano-twinned copper layer includes plural twinned grains. Furthermore, a substrate including the aforesaid nano-twinned copper layer and a method for preparing the aforesaid nano-twinned copper layer are also disclosed.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 24, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chih Chen, Kang-Ping Lee
  • Patent number: 11563047
    Abstract: The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 24, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Wen-Hsien Chen
  • Patent number: 11560598
    Abstract: The invention provides oncogenomic methods for detecting tumors by identifying circulating tumor DNA. A patient-specific reference directed acyclic graph (DAG) represents known human genomic sequences and non-tumor DNA from the patient as well as known tumor-associated mutations. Sequence reads from cell-free plasma DNA from the patient are mapped to the patient-specific genomic reference graph. Any of the known tumor-associated mutations found in the reads and any de novo mutations found in the reads are reported as the patient's tumor mutation burden.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 24, 2023
    Assignee: Seven Bridges Genomics Inc.
    Inventors: Wan-Ping Lee, Devin Locke
  • Publication number: 20230018242
    Abstract: The present invention relates to a kit of in vitro quantifying large surface protein of hepatitis B virus (LHBS). The kit includes monoclonal antibodies having respective binding specificity for specific regions of LHBS, thereby increasing sensitivity and dynamic breadth of detecting LHBS in a biological sample. Moreover, the invention also provides a biomarker set corresponding to the specific regions of LHBS, and the biomarker set can be specifically recognized by the monoclonal antibodies, for non-invasively analyzing phases of HBV infection and hepatoma prognosis in a biological sample. Furthermore, the invention also provides a set of monoclonal antibodies for predicting, diagnosing or treating a chronic liver disease via those biomarkers in a subject in need thereof.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 19, 2023
    Inventors: Wen Ya HUANG, Chia Jui YEN, Yun-Ping LEE
  • Publication number: 20230014827
    Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. Rhe ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Inventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
  • Patent number: 11548031
    Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 10, 2023
    Assignee: SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
  • Patent number: 11548171
    Abstract: A robot arm including a first joint, a second joint, and a coupling element is provided. The first joint has a first inclined surface. The second joint is jointed to the first joint and has a second inclined surface. The coupling element has a third inclined surface and a fourth inclined surface opposite to the third inclined surface, wherein the third inclined surface contacts the first inclined surface, and the fourth inclined surface contacts the second inclined surface.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: January 10, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ping Lee, Hen-Diong Kng, Hao-Yan Wu, Tsang-Fang Jeng, Shu Huang, Hung-Hsiu Yu
  • Publication number: 20220406933
    Abstract: A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region in the first well region, the deep drain doped region has the first conductivity type.
    Type: Application
    Filed: September 30, 2021
    Publication date: December 22, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hirokazu Fujimaki, Bo-An Tsai, Shih-Ping Lee
  • Publication number: 20220401661
    Abstract: A droplet delivery device includes a housing with a mouthpiece port or outlet from a nasal device for releasing fluid droplets, a fluid reservoir, and an ejector bracket having a membrane positioned between a mesh with a plurality of openings and a vibrating member that is coupled to an electronic transducer, such as an ultrasonic transducer. The transducer vibrates the vibrating member which causes the membrane to push fluid supplied by the reservoir through the mesh to generate droplets in an ejected stream released through the outlet.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 22, 2022
    Applicant: PNEUMA RESPIRATORY, INC.
    Inventors: Charles Eric Hunter, Michael Scoggin, Jeffrey Miller, Jose Salazar, Brian Beach, Caley Modlin, Matthew Culpepper, Jianqiang Li, Chengjie Li, Shi Bo Wang, Chao-Ping Lee, Gregory Rapp, Judson Sidney Clements
  • Patent number: 11527564
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: December 13, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20220393012
    Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate, wherein the fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming an isolation feature around the fin, forming a dielectric feature over the isolation feature, forming a cap layer over the fin and the dielectric feature, oxidizing the cap layer to form an oxidized cap layer, forming source/drain features passing through the cap layer and in the fin, removing the second semiconductor layers in the fin to form nanostructures, and forming a gate structure wrapping around the nanostructures.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Fan PENG, Yuan-Ching PENG, Yu-Bey WU, Yu-Shan LU, Ying-Yan CHEN, Yi-Cheng LI, Szu-Ping LEE
  • Publication number: 20220384251
    Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: I-Ping LEE, Kwang-Ming LIN, Chih-Cherng LIAO, Ya-Huei KUO, Pei-Yu CHANG, Ya-Ting CHANG, Tsung-Hsiung LEE, Zheng-Xian WU, Kai-Chuan KAN, Yu-Jui CHANG, Yow-Shiuan LIU
  • Publication number: 20220344398
    Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.
    Type: Application
    Filed: July 10, 2022
    Publication date: October 27, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Patent number: 11478822
    Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. The ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 25, 2022
    Assignees: J-Metrics Technology Co., Ltd., Peking University Shenzhen Graduate School
    Inventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
  • Patent number: 11469229
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration in a range of 5% to 30%; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer to a range of 1% to 5%; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Szu-Ping Lee, Che-Hao Chang, Chun-Heng Chen, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11460341
    Abstract: A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 4, 2022
    Assignees: j-Metrics Technology Co., Ltd., Peking University Shenzhen Graduate School
    Inventors: Yu-Feng Jin, Sheng-Lin Ma, Yi-Hsiang Chiu, Hung-Ping Lee, Dan Gong
  • Publication number: 20220289384
    Abstract: A unit load device (ULD) for aircraft cargo loading, the ULD including a container having a cargo portion and a ledge extending from the cargo portion. The ledge is configured to interface with a floor latch. A first latch sensor is disposed on the ledge. The first latch sensor is configured to detect a closed latch contact. A controller is electrically connected to the first sensor, and is configured to automatically perform an action in response to the first latch sensor detecting the closed latch contact.
    Type: Application
    Filed: February 23, 2022
    Publication date: September 15, 2022
    Inventor: Shaw Ping Lee