Patents by Inventor Po-Jen Cheng
Po-Jen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10230109Abstract: An electrical or electrochemical cell, including a cathode layer, an electrolyte layer, and an anode layer is disclosed. The cathode layer includes a first material providing a cathodic electric transport, charge storage or redox function. The electrolyte layer includes a polymer, a first electrolyte salt, and/or an ionic liquid. The anode layer includes a second material providing an anodic electric transport, charge storage or redox function. At least one of the cathode and anode layers includes the ionic liquid, a second electrolyte salt, and/or a transport-enhancing additive.Type: GrantFiled: February 23, 2016Date of Patent: March 12, 2019Assignee: Imprint Energy, Inc.Inventors: John Devin MacKenzie, Christine Chihfan Ho, Karthik Yogeeswaran, Po-Jen Cheng
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Patent number: 9276292Abstract: An electrical or electrochemical cell, including a cathode layer, an electrolyte layer, and an anode layer is disclosed. The cathode layer includes a first material providing a cathodic electric transport, charge storage or redox function. The electrolyte layer includes a polymer, a first electrolyte salt, and/or an ionic liquid, The anode layer includes a second material providing an anodic electric transport, charge storage or redox function. At least one of the cathode and anode layers includes the ionic liquid, a second electrolyte salt, and/or a transport-enhancing additive.Type: GrantFiled: March 15, 2013Date of Patent: March 1, 2016Assignee: Imprint Energy, Inc.Inventors: John Devin MacKenzie, Christine Chihfan Ho, Karthik Yogeeswaran, Po-Jen Cheng
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Patent number: 8288853Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.Type: GrantFiled: November 10, 2009Date of Patent: October 16, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Patent number: 7863181Abstract: Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched.Type: GrantFiled: July 9, 2008Date of Patent: January 4, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsueh An Yang, Po Jen Cheng
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Patent number: 7741152Abstract: A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.Type: GrantFiled: December 26, 2006Date of Patent: June 22, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Publication number: 20100052136Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.Type: ApplicationFiled: November 10, 2009Publication date: March 4, 2010Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Publication number: 20100048246Abstract: The invention includes a mobile communication apparatus and an audio switching method. The mobile communication apparatus according to the invention includes a receiver, a speaker, an optoelectronic sensing component, and a control unit. The optoelectronic sensing component is used to sense an environment state and generate an optical detection signal representing a result of sensing the environmental state. The control unit is coupled to the receiver, the speaker, and the optoelectronic sensing component. And, the control unit receives the optical detection signal and selectively outputs an audio signal via the receiver or the speaker according to the optical detection signal.Type: ApplicationFiled: April 27, 2009Publication date: February 25, 2010Inventors: Ming YIN, Po-Jen Cheng
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Patent number: 7642132Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages.Type: GrantFiled: October 23, 2006Date of Patent: January 5, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Publication number: 20090300849Abstract: The present invention relates to a method of extracting oil of cloth via supercritical fluid, comprises the steps of: a cloth to be extracted is provided in an extracting tank; a gas is filled into a storing tank; a water-cooling machine is provided and served to cool down the temperature of the gas; a pump is provided and served to compress the gas; a water-heating machine is provided and served to raise the temperature of the gas so the gas becomes a supercritical fluid; and the supercritical fluid is inserted into the extracting tank for extracting the oil. By the above mentioned method, the cleanness of the cleanroom wiping cloth can be immediately sensed and obtained, and the gas can be recycled for achieving energy-saving.Type: ApplicationFiled: April 27, 2009Publication date: December 10, 2009Inventors: Po-Jen Cheng, Li-Hao Cheng, Chih-Huang Cheng
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Patent number: 7528053Abstract: A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.Type: GrantFiled: December 26, 2006Date of Patent: May 5, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Patent number: 7501342Abstract: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.Type: GrantFiled: March 18, 2008Date of Patent: March 10, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Wei Chung Wang, Po Jen Cheng, Hsueh An Yang, Pei Chun Chen
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Patent number: 7500122Abstract: An efficiency optimization method for hardware devices with adjustable clock frequencies is provided. The work current of the hardware device is measured and used to obtain the corresponding work level from a conversion table. The obtained work level is compared with the currently executing work level to make adjustments for various parameters for the hardware device and for the operation of the corresponding heat-dissipating device. Therefore, the hardware device can achieve a better performance.Type: GrantFiled: January 20, 2006Date of Patent: March 3, 2009Assignee: Micro-Star Int'l Co., Ltd.Inventors: Ming-Ting Won, Fu-Shun Wu, Po-Jen Cheng
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Publication number: 20090047782Abstract: Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched.Type: ApplicationFiled: July 9, 2008Publication date: February 19, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsueh An YANG, Po Jen CHENG
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Publication number: 20080303167Abstract: A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.Type: ApplicationFiled: March 18, 2008Publication date: December 11, 2008Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei Chung WANG, Po Jen CHENG, Hsueh An YANG, Pei Chun CHEN
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Patent number: 7446404Abstract: A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.Type: GrantFiled: December 26, 2006Date of Patent: November 4, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Patent number: 7297080Abstract: A game racquet includes head portion and a handle portion. The head and handle portions include one or both of a fiber-reinforced thermoset material and a fiber-reinforced thermoplastic material. The handle portion is coupled to the head portion by shock and/or vibration absorbing material.Type: GrantFiled: January 6, 2005Date of Patent: November 20, 2007Assignee: Wilson Sporting Goods Co.Inventors: William D. Severa, Po-Jen Cheng, Gerald J. LeVault, Donald G. Loeffler
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Publication number: 20070172982Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages.Type: ApplicationFiled: October 23, 2006Publication date: July 26, 2007Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Publication number: 20070172985Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a metal; (g) removing the dry film, and patterning the conductive layer; (h) removing a part of the metal in the blind hole to form a space; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; (k) stacking a plurality of the wafers, and performing a reflow process; and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.Type: ApplicationFiled: December 26, 2006Publication date: July 26, 2007Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chain-Chi Lin
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Publication number: 20070172986Abstract: The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal.Type: ApplicationFiled: December 26, 2006Publication date: July 26, 2007Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
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Publication number: 20070172984Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.Type: ApplicationFiled: December 26, 2006Publication date: July 26, 2007Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin