Abstract: A micro-light-emitting diode chip includes an epitaxial structure, an electrode, a transparent structure, and a reflection layer. The epitaxial structure has a light exit surface, a back surface opposite to the light exit surface, and a sidewall surface. The sidewall surface is connected to the light exit surface and the back surface. The electrode is electrically coupled to the epitaxial structure. The transparent structure has an inner surface and an outer surface opposite to the inner surface. The inner surface is connected to the sidewall surface. A distance between the outer surface and the inner surface on a plane where the back surface is located is less than a distance between the outer surface and the inner surface on a plane where the light exit surface is located. The reflection layer is in direct contact with the outer surface. A micro-light-emitting diode display is also provided.

Abstract: A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor and a control circuit. The control circuit is coupled to the set of memory cells, the cycle transistor and the reference transistor. A method of controlling the non-volatile memory device includes in a program operation or an erase operation of the set of memory cells, the control circuit determining a state of the cycle transistor, and upon determining the cycle transistor being in an erased state (or a programmed state), the control circuit setting the reference transistor from a reference state to the erased state (or the programmed state), and then restoring the reference transistor from the erased state (or the programmed state) to the reference state. The reference state is set between the erased state and a programmed state.

Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.

Abstract: A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.

Abstract: A beam splitting and combining device includes a first prism, a second prism and a first optical film. The first prism includes a first surface, a second surface and a third surface. The second prism includes a fourth surface, a fifth surface and a sixth surface. The fifth surface and the second surface are attached to each other. The first optical film is formed between the second surface and the fifth surface by coating. A beam in a first range of wavelengths is configured to pass through the first surface, the second surface, the first optical film, the fifth surface and the sixth surface in order or in reverse order, or is configured to pass through the first surface and the third surface in order or in reverse order.

Abstract: An adjustable stand for an electronic device that is operable for stable movement in two directions with the use of a single hand of a user. An ergonomic design leverages a natural and intuitive movement of a user's hand to maintain an orientation of the electronic device throughout at least 180 degrees of movement.

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Abstract: A method for manufacturing a circuit board includes disposing an electronic component in a recess formed in a first circuit substrate, and bonding a second circuit substrate to the first circuit substrate to form a third circuit substrate with the electronic component embedded. The method includes forming an opening in the third circuit substrate to expose the electronic component and an inner surface of the third circuit substrate. The method includes disposing an insulation case in the opening. The insulation case has a first segment directly contacting the electronic component, a second segment facing the inner surface, an inner wall between the first and second segments, a first chamber surrounded by the first segment and the inner wall, and a second chamber surrounded by the second segment and the inner wall. The method includes adding a heat-exchanging fluid into the first chamber.

Abstract: An optimizing method and a computing apparatus for a deep learning network and a computer-readable storage medium are provided. In the method, a value distribution is obtained from a pre-trained model. One or more breaking points in a range of the value distribution are determined. Quantization is performed on a part of values of a parameter type in a first section among multiple sections using a first quantization parameter and the other part of values of the parameter type in a second section among the sections using a second quantization parameter. The value distribution is a statistical distribution of values of the parameter type in the deep learning network. The range is divided into the sections by one or more breaking points. The first quantization parameter is different from the second quantization parameter. Accordingly, accuracy drop can be reduced.

Abstract: A color filter array includes a first color resist, a second color resist, and a third color resist. The first color resist has a first color, the second color resist has a second color, and the third color resist has a third color. A transparency of the third color resist is greater than transparencies of the first color resist and the second color resist. The first color resist has a first edge and a second edge arranged along a first direction. The second color resist has a first edge and a second edge arranged along a first direction. The first color resist and the second color resist are arranged along a second direction. The first edge of the first color resist, the second edge of the second color resist, and the second edge of the first color resist are arranged sequentially along the first direction.

Abstract: This invention relates to a surface coating for capture circulating rare cells, comprising a nonfouling composition to prevent the binding of non-specific cells and adsorption of serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the nonfouling and bioactive compositions. The invention also provide a surface coating for capture and purification of a biological substance, comprising a releasable composition to release the non-specific cells and other serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the releasable and bioactive compositions. The present invention also discloses a novel microfluidic chip, with specific patterned microstructures to create a flow disturbance and increase the capture rate of the biological substance.

Abstract: A wide-angle lens assembly includes a first lens including negative refractive power and a concave surface, a second lens including a meniscus lens with negative refractive power, a third lens, a fourth lens including positive refractive power and a convex surface, a fifth lens including a biconvex lens, a sixth lens including a biconvex lens, a seventh lens including positive refractive power and a convex surface, an eighth lens including a biconcave lens, a ninth lens including negative refractive power, and a stop disposed between the fourth lens and the sixth lens. The eighth lens is disposed between the fifth and seventh lenses and is cemented with at least one lens. The ninth lens is disposed between the fifth lens and an image side. The wide-angle lens assembly satisfies 1.3<A/IH<2.1 where A is a diameter of the stop and 1H is a maximum image height of the wide-angle lens assembly.

Abstract: A method for processing a substrate is provided. The method includes the following operations: placing a substrate over a first injector in a substrate processing apparatus, the substrate having a front surface and a back surface opposite to the front surface, and the front surface having a plurality of concentric regions; adjusting a temperature of each of the plurality of concentric regions by controlling at least one of a flow rate and a temperature associated with a fluid dispensing from the first injector; and rotating the substrate by a spin base disposed below the substrate, the substrate is rotated with respect to a center axis perpendicular to the front surface thereof when adjusting the temperature. The spin base includes a ring opening for rotating relative to the first injector, and the first injector is displaced from a projection of a center of the substrate from a top view perspective.

Abstract: A reflective display device includes an electrophoretic display (EPD) module, an optical layer, a color filter layer, and at least one quantum dot (QD). The optical layer is located above the electrophoretic display module. The color filter layer is located on the optical layer. The quantum dot is located between the optical layer and the electrophoretic display module. When first light passes through the optical layer and transmits to the quantum dot, the quantum dot emits second light, and the electrophoretic display module is configured to reflect the second light to irradiate outwards from the color filter layer.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A graph application programming interface (API) is used to control an image processing flow. A system receives graph API calls to add nodes to respective subgraphs. The system further receives a given graph API call to add a control flow node to a main graph. The given graph API call identifies the subgraphs as parameters. The main graph includes the control flow node connected to other nodes by edges that are directed and acyclic. A graph compiler compiles the main graph and the subgraphs into corresponding executable code. At runtime, a condition is evaluated before the subgraphs identified in the given graph API call are executed. One or more target devices execute the corresponding executable code to perform operations of an image processing pipeline while skipping execution of one or more of the subgraphs depending on the condition.

Abstract: An image processing system includes one or more processors operative to receive a graph application programming interface (API) call to add a complex node to a graph. The graph includes at least the complex node connected to other nodes by edges that are directed and acyclic. The one or more processors are further operative to process, by a graph compiler at compile time, the complex node by iteratively expanding the complex node into multiple nodes with each node corresponding to one operation in an image processing pipeline. The system further includes one or more target devices to execute executable code compiled from each node to perform operations of the image processing pipeline. The system further includes memory to store the graph compiler and the executable code.

Abstract: A color electrophoretic display includes a display region, a pixel array, a display medium layer, an optical layer, a first color filter array, and a second color filter array. The display region includes multiple sub-pixel regions. The pixel array corresponds to the display region in position. The display medium layer is located on the pixel array. The optical layer is located on the display medium layer. The first color filter array is located on the optical layer. The second color filter array is located between the display medium layer and the optical layer.