Patents by Inventor Po Yuan

Po Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230172472
    Abstract: A biological energy signal acquisition and conversion device comprises: a signal acquisition module, enhancing a biological energy signal generated by an original biological energy body, and extracting the signal; a signal processing module, receiving the extracted original biological energy signal and filtering and amplifying the signal, and generating an output energy signal; and a signal output unit, being able to enhance an output function in cooperation with a magnetic substance, and output the energy signal to a biological energy carrier. By shortening the distance between the original biological energy body and a signal receiving unit, and using the magnetic substance to excite the original biological energy body, the strength of the received extracted original biological energy signal is enhanced, and the noise proportion is greatly reduced, reducing the technical complexity and costs for back-end signal processing, and improving the effect of a biological energy signal.
    Type: Application
    Filed: August 28, 2019
    Publication date: June 8, 2023
    Inventors: Chun-Fang Cheng, Ting-Han Hong, Po-Yuan Kung, Jia-De Ni, Hsun-Tsan Shen, Wen-Chun Yeh
  • Publication number: 20230154865
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 18, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Patent number: 11646296
    Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Patent number: 11646255
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang
  • Publication number: 20230137400
    Abstract: A smart dialing recommendation method, a non-transitory computer-readable medium, and a mobile device are disclosed. The smart dialing recommendation method includes: establishing a database according to a correspondence between a plurality of different time intervals in a past time range and a plurality of communication numbers by using a machine learning algorithm; obtaining a time stamp; and determining whether the time stamp has expired. When it is determined that the time stamp has not expired, according to the correspondence in the database and a current time point, a recommended number corresponding to the current time point is retrieved from the plurality of communication numbers. When it is determined that the time stamp has expired, the machine learning algorithm is performed again to update the plurality of communication numbers.
    Type: Application
    Filed: September 30, 2022
    Publication date: May 4, 2023
    Inventors: Po-Yuan Shih, Cheng-Ming Chen
  • Publication number: 20230120191
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Publication number: 20230109682
    Abstract: A message management method based on time and location is applied to the network system. Comprises obtaining a user account, a location information and a time information through an electronic device, and transferring the user account, the location information and the time information to a message server; obtaining a geographic information from a map database based on the location information, and displaying a region of the geographic information on a display of the electronic device; and in a display page of the display, using the user account, the time information and the region as a filter condition, obtaining a name, an avatar of a relevant user from a user database, and obtaining a message of the relevant user from a message database, and displaying the name, avatar and message of the relevant user on the display page according to the sending location of the message.
    Type: Application
    Filed: March 9, 2020
    Publication date: April 13, 2023
    Inventor: PO-YUAN LIU
  • Patent number: 11627668
    Abstract: A circuit board includes a circuit substrate, a solder, and a surrounding portion. The circuit substrate includes a connecting pad. The solder is formed on a surface of the connecting pad. The surrounding portion is formed on the surface of the connecting pad and cooperates with the connecting pad to form a groove receiving the solder. The surrounding portion surrounds the solder and is spaced from the solder. A method for manufacturing a circuit board is also provided.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: April 11, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Yong-Chao Wei, Po-Yuan Chen
  • Publication number: 20230103560
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Application
    Filed: November 14, 2022
    Publication date: April 6, 2023
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Patent number: 11606862
    Abstract: A circuit board includes a circuit substrate, at least one metal pad, and a tin bar corresponding to each of the at least one metal pad. Each of the at least one metal pad is formed on a side of the circuit substrate and is electrically connected to the circuit substrate. A surface of the metal pad facing away from the circuit substrate is recessed toward the circuit substrate to from a recess. The tin bar is received in the recess. A method for manufacturing a circuit board is also provided.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 14, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Po-Yuan Chen, Yong-Chao Wei
  • Publication number: 20230065884
    Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20230055238
    Abstract: A vehicle risk analysis system, includes: a historical database, storing the sensing data and accident records acquired from multiple sampled vehicles into big data; a learning unit, connected to the historical database for analyzing the relationship between accident records and driving scenarios, to generate a risk classification model, which can further predict the risk of accidents for a vehicle in-use; and a risk profiling unit, receiving the risk classification model from the learning unit and acquiring the sensing data from the vehicle in-use, to generate a risk profile for the vehicle in-use under different driving modes. The risk profile reports the expected risks of accidents under different driving modes by using the occurrence rates for different driving scenarios and the expected losses of money caused by accidents, wherein each of the driving scenarios can be determined by a combination of the sensing data.
    Type: Application
    Filed: March 29, 2022
    Publication date: February 23, 2023
    Inventor: Po-Yuan Chen
  • Patent number: 11588041
    Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
  • Patent number: 11569202
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Publication number: 20230026141
    Abstract: A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Publication number: 20230027261
    Abstract: A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Tzu Ang Chiang, Chun-Neng Lin, Jian-Jou Lian, Chieh-Wei Chen, Ming-Hsi Yeh, Po-Yuan Wang
  • Patent number: 11561323
    Abstract: An intelligent storage device and an intelligent storage method are provided. The intelligent storage device includes a storage space, an infrared sensor, a weight sensor, a transceiver, and a processor. The storage space is suitable for storing an object. The infrared sensor senses the storage space to generate infrared sensing data. The weight sensor senses the object in the storage space to generate weight sensing data. The processor is coupled to the infrared sensor, the weight sensor, and the transceiver, determines whether the object is placed in or removed from the storage space according to the infrared sensing data and the weight sensing data to generate an event record, and transmits the event record via the transceiver.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 24, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Hsin-Chien Huang, Po-Yuan Hsiao, Chu-An Chung, Wen Tsui, Chi-Chou Chiang
  • Patent number: 11561448
    Abstract: A front plate laminate structure includes a display medium layer, a top adhesive layer, a transparent substrate, a transparent conductive film, and a color filter layer. The top adhesive layer is located on the display medium layer. The transparent substrate is located on the top adhesive layer. The transparent conductive film is located between the transparent substrate and the top adhesive layer. The transparent conductive film includes a bottom surface facing the top adhesive layer. The color filter layer is located between the transparent substrate and the display medium layer.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 24, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Jau-Min Ding, Po-Yuan Lo, Sheng-Long Lin, Ian French
  • Publication number: 20230014913
    Abstract: In an embodiment, a device includes: a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component, the integrated circuit die exposed at a back-side of the package component; a heat dissipation layer on the back-side of the package component and on sidewalls of the package component; an adhesive layer on a back-side of the heat dissipation layer, a portion of a sidewall of the heat dissipation layer being free from the adhesive layer; and a package substrate connected to the conductive connectors.
    Type: Application
    Filed: March 4, 2022
    Publication date: January 19, 2023
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Publication number: 20220415737
    Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Wu, Ting Hao Kuo, Kuo-Lung Pan, Po-Yuan Teng, Yu-Chia Lai, Shu-Rong Chun, Mao-Yen Chang, Wei-Kang Hsieh, Pavithra Sriram, Hao-Yi Tsai, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo