Abstract: Disclosed herein are methods for performing assays, including general functional assays, on a biological cell. Also disclosed herein are methods of barcoding the 5? ends of RNA from a biological cell and methods of preparation of expression constructs from the barcoded RNA. The barcoded RNA can encode proteins of interest, such as B cell receptor (BCR) heavy and light chain sequences. The expression constructs can be generated individually or in a paired/multiplexed manner, allowing rapid re-expression of individual proteins or protein complexes.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A lens assembly includes a first lens, a second lens, and a third lens arranged sequentially from an object side to an image side along an optical axis. The first lens has positive refractive power. The second lens has a convex surface facing the image side and negative refractive power. The third lens has a convex surface facing the object side and negative refractive power. The lens assembly satisfies at least one of the following conditions: 2<f/D1<3.5; ?3<f3/f<?1; 0.5 mm<D1+D3<2.4 mm; 0.7<f1/D1<2; wherein f is an effective focal length of the lens assembly, D1 is a maximum effective optical diameter of the first lens, D3 is a maximum effective optical diameter of the third lens, and f1 and f3 are an effective focal length of the first lens and the third lens, respectively.

Abstract: A package structure includes first and second package components, an underfill layer disposed between the first and second package components, and a metallic layer. The first package component includes semiconductor dies, a first insulating encapsulation laterally encapsulating the semiconductor dies, and a redistribution structure underlying first surfaces of the semiconductor dies and the first insulating encapsulation. The second package component underlying the first package component is electrically coupled to the semiconductor dies through the redistribution structure. The underfill layer extends to cover a sidewall of the first package component, the metallic layer overlying second surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the second surface of the first insulating encapsulation is accessibly exposed by the metallic layer, where the first surfaces are opposite to the second surfaces.

Abstract: An optical virtual push button touch panel includes a substrate (10), a light emitting member (11), a light guide plate (12), a light permeable plate (13), and a touch control sensing member (14). The substrate is provided with a mounting slot (100). The light emitting member is mounted in the substrate. The light guide plate defines multiple light guide structures (120). The light permeable plate is mounted on the substrate. The touch control sensing member is located between the light permeable plate and the light guide plate and defines multiple contact zones (140) aligning with the light guide structures respectively. One of the contact zones produces a coupling capacitance through the light permeable plate and drives the light emitting member to generate the light source, and one of the light guide structures converges the light source toward one of the contact zones.

Abstract: A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A communication device includes a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a fifth antenna element, a sixth antenna element, a seventh antenna element, an eighth antenna element, and a PCB (Printed Circuit Board). The PCB has a first side and a second side positioned opposite to each other. At least one of the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, the sixth antenna element, the seventh antenna element, and the eighth antenna element is adjacent to the first side of the PCB. The other(s) of the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, the sixth antenna element, the seventh antenna element, and the eighth antenna element is/are adjacent to the second side of the PCB.

Abstract: The color filter array includes multiple first color resist, multiple second color resists, and second color resists third color resists. The first color resist have a first color. The second color resists have a second color different from the first color. The third color resists have a third color different from the first color and second color. A reflectance of the third color resists is greater than a reflectance of the first color resists and a reflectance of the second color resists, the first color resists are continuously arranged along a first diagonal direction and a second diagonal direction, and the third color resists are not arranged along the second diagonal direction continuously.

Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.

Abstract: The color electrophoretic display includes a display region, a pixel array, a display medium layer, and a color filter array. The display region includes multiple sub-pixel regions. The pixel array corresponds to the display region in position. The display medium layer is located on the pixel array. The color filter array is located on the display medium layer. The color filter array includes multiple color resists. A portion of the color resists include a first pixel fill factor, another portion of the color resists include a second pixel fill factor, the second pixel fill factor is smaller than the first pixel fill factor, and the first pixel fill factor and the second pixel fill factor are smaller than 60%.

Abstract: A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.

Abstract: A calibrating device includes a memory and a processor. The memory is configured to store at least one computer readable instruction. The processor is electrically coupled to the memory, and configured to access and execute the at least one computer readable instruction to: analyze an image of a target region which a seam between two LED panels disposed side by side is in, to obtain characteristic data associated with the seam; compare the characteristic data associated with the seam with a predetermined value to generate a comparison result; and adjust grayscale data of pixels which are arranged in two lines of the two LED panels and adjacent to the seam, based on the comparison result, for adjusting luminance-chromaticity of the pixels, wherein the two lines are in a first direction or a second direction, and the first direction is perpendicular to the second direction.

Abstract: A communication device includes a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a fifth antenna element, a sixth antenna element, a seventh antenna element, an eighth antenna element, and a PCB (Printed Circuit Board). The PCB has a first side and a second side positioned opposite to each other. At least one of the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, the sixth antenna element, the seventh antenna element, and the eighth antenna element is adjacent to the first side of the PCB. The other(s) of the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, the sixth antenna element, the seventh antenna element, and the eighth antenna element is/are adjacent to the second side of the PCB.

Abstract: A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Abstract: A color filter array includes a first color resist having a first color, a second color resist having a second color different from the first color, and a third color resist having a second color different from the first color and the second color. The first color resist includes multiple sections. The second color resist includes multiple sections. The third color resist includes multiple sections. When viewed in a plan view, the sections of the first color resist collectively arranged as a continuous S shape, the sections of the second color resist collectively arranged as a continuous S shape, and the sections of the third color resist collectively arranged as a continuous S shape.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. An original image of the display is received and segmented into region of interest (ROI) patches. A predetermined range of spatial frequency components are filtered out from the ROI patches to generate filtered ROI patches. A mura defect is identified from the display according to the filtered ROI patches and predetermined mura patterns.

Abstract: This invention relates to a surface coating for capture circulating rare cells, comprising a nonfouling composition to prevent the binding of non-specific cells and adsorption of serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the nonfouling and bioactive compositions. The invention also provide a surface coating for capture and purification of a biological substance, comprising a releasable composition to release the non-specific cells and other serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the releasable and bioactive compositions. The present invention also discloses a novel microfluidic chip, with specific patterned microstructures to create a flow disturbance and increase the capture rate of the biological substance.