Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display panel (20) and a flexible circuit board electrically connected with the display panel (20). The flexible circuit board includes a first circuit board (11), a second circuit board (22) and a conductive portion; the first circuit board (11) includes a first substrate (100), and a main contact pad, a first wire (501) and a second wire (502) provided on the first substrate (100); the second circuit board (22) includes a second substrate (200), a relay contact pad and a third wire (210) provided on the second substrate (200); and the conductive portion is configured for electrically connecting the main contact pad and the relay contact pad.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.

Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

Abstract: The present invention provides a display module and a display device. The display module comprises a display panel and heat dissipation structure; the display panel comprises a substrate, and a display substrate layer located on the substrate; the heat dissipation structure is located on the side of the substrate distant from the display substrate layer; and a gap is formed between at least part of the region of the heat dissipation structure and the substrate. The display module provided by the present invention improves the heat dissipation efficiency of the display panel.

Abstract: A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: Some embodiments of the invention provide a method of sending data in a network that includes multiple worker nodes, each worker node executing at least one set of containers, a gateway interface, and a virtual local area network (VLAN) tunnel interface. The method configures the gateway interface of each worker node to associate the gateway interface with multiple subnets. Each subnet is associated with a namespace, a first worker node executes a first set of containers of a first namespace, and a second worker node executes a second set of containers of the first namespace and a third set of containers of a second namespace. The method sends data between the first set of containers and the second set of containers through a VLAN tunnel between the first and second worker nodes. The method sends data between the first set of containers and the third set of containers through the gateway interface.

Abstract: Some embodiments of the invention provide a method of sending data in a network that includes at least one worker node executing one or more sets of containers and a virtual switch, the virtual switch including a gateway interface, a virtual local area network (VLAN) tunnel interface, and a set of virtual Ethernet interfaces associated with the one or more sets of containers. The method configures the gateway interface of the worker node to associate the gateway interface with multiple subnets that are each associated with a namespace. The worker node executes at least (1) first and second sets of containers of a first namespace, and (2) a third set of containers of a second namespace. The method sends data between the first and second sets of containers through a first virtual Ethernet interface associated with the first set of containers and a second virtual Ethernet interface associated with the second set of containers.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display panel and a flexible circuit board electrically connected with the display panel. The flexible circuit board includes a first circuit board, a second circuit board and a conductive portion; the first circuit board includes a first substrate, and a main contact pad, a first wire and a second wire provided on the first substrate; the second circuit board includes a second substrate, a relay contact pad and a third wire provided on the second substrate; and the conductive portion is configured for electrically connecting the main contact pad and the relay contact pad.

Abstract: Described in detail herein is a system for determining the validity of a transaction in a distributed network environment. The system includes a plurality of peer servers. The system elects a set of peer leaders from the plurality of peer servers. The set of peer leaders broadcast a first set of indices associated with a first subset of transactions, received from the plurality of peer servers, to one or more of the plurality of peer servers. The set of elected peer leaders execute a first instance of a binary agreement protocol based at least in part on a second subset of indices associated with a second subset of the transactions. The set of elected peer leaders output a consensus vector comprising one or more of the transactions.

Abstract: Described in detail herein is a system for determining the validity of a transaction in a distributed network environment. The system includes a plurality of peer servers. The system broadcast a first transaction to the plurality of peer servers. The system further elects at least one peer leader from the plurality of peer servers. The system further broadcasts a first set of indices associated with a first subset of transactions, received from the plurality of peer servers, to one or more of the plurality of peer servers. The system further executes a first instance of a binary agreement protocol based at least in part on a second subset of indices associated with a second subset of the transactions. The system further outputs a consensus vector comprising one or more of the transactions.

Abstract: Methods and systems for fully-automatic image processing to detect and remove unwanted people from a digital image of a photograph. The system includes the following modules: 1) Deep neural network (DNN)-based module for object segmentation and head pose estimation; 2) classification (or grouping) of wanted versus unwanted people based on information collected in the first module; 3) image inpainting of the unwanted people in the digital image. The classification module can be rules-based in an example. In an example, the DNN-based module generates, from the digital image: 1. A list of object category labels, 2. A list of object scores, 3. A list of binary masks, 4. A list of object bounding boxes, 5. A list of crowd instances, 6. A list of human head bounding boxes, and 7. A list of head poses (e.g., yaws, pitches, and rolls).

Abstract: A circuit board assembly includes a connection circuit board, a near field communication antenna and solders. The connection circuit board includes circuit board pads. The near field communication antenna is attached to the connection circuit board, and the near field communication antenna includes: an antenna coil, antenna pads electrically connected to the antenna coil, and through holes penetrating the antenna pads and disposed opposite to the circuit board pads. The solders are connected to the circuit board pads through the through holes.

Abstract: Embodiments of a peak power management (PPM) circuit on a memory die are disclosed. The PPM circuit includes a first transistor and a second transistor arranged in parallel, wherein the first and second transistors each has a drain terminal electrically connected to a first power source and a second power source, respectively. The PPM circuit also includes a resistor having a first terminal electrically connected to respective source terminals of the first and second transistors. The PPM circuit further includes a first contact pad on the memory die, electrically connected to a second contact pad on a different memory die through a die-to-die connection. The PPM circuit also includes a third transistor with a drain terminal electrically connected to a second terminal of the resistor, and a source terminal electrically connected to the first contact pad.

Abstract: A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.

Abstract: A curved surface lamination device, comprising a profiling jig (01), the profiling jig (01) comprising a base (101) and a profiling portion (102), with the profiling portion (102) being configured to support a carrier film (02), and the side of the base (101) facing away from the profiling portion (102) being provided with an opening; and a lower jig (03), comprising a first sinking groove (301), with part of the base (101) being inserted into the first sinking groove (301), such that the lower jig (03) encloses a hollow structure (E) with the base (101) at the opening position.

Abstract: This disclosure provides for methods and a system for multiple instance segmentation and tracking. According to an aspect a method is provided. The method includes sending an image to a backbone network and generating image feature outputs. The method further includes sending the image feature outputs to a spatial attention module for generating a feature map associated with objects in the image. The method further includes sending the feature map to a category feature module for generating an instance category output indicating the objects. The method further includes sending the image feature outputs to a mask generating module for generating masks. The method further includes generating: the instance category output via the category feature module, and the masks via the mask generating module. In some embodiments, the method further includes generating re-identification embedding information associated with the objects based on image feature outputs.

Abstract: A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.

Abstract: The disclosure provides a method and a device for measuring a cutting force, an electronic apparatus and a storage medium. The method includes: obtaining first cutting force data of a cutter of a craft equipment, first torque data of a first servo motor, and second torque data of a second servo motor in a case that the cutting force of the craft equipment is detected to be in a stable state; generating first cutting force compensation data based on a first torque mapping coefficient and the first torque data; generating second cutting force compensation data based on a second torque mapping coefficient and the second torque data; and correcting the first cutting force data based on the first cutting force compensation data and the second cutting force compensation data to obtain target cutting force data.