Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

Abstract: A method of peak power management (PPM) for a memory chip with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the memory chip; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

Abstract: The present disclosure relates to the technical field of display product preparation, and in particular discloses a flexible display panel lamination device which is used for laminating a to-be-laminated flexible display panel onto a cover plate, and includes a base and an elastic lamination part arranged on the base. The elastic lamination part is provided with a first surface for bearing the to-be-laminated flexible display panel and a second surface opposite to the first surface; the second surface is symmetrically provided with two supporting protruding ribs; the two supporting protruding ribs are respectively fixed in two fixation grooves formed on the base; a gap is formed between a portion, located between the two supporting protruding ribs, of the second surface of the elastic lamination part and the base; and a portion, close to the edge, of the second surface of the elastic lamination part is supported on the base.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. P redundant banks are included in and shared by the P groups of banks. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. The I/O control logic is configured to determine the P×N working banks from the P groups of banks based on bank fail information indicative of K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. The I/O control logic is also configured to control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes a first-level memory unit which includes a plurality of second-level memory units. Each second-level memory unit includes N main banks and a redundant bank, where N is a positive integer. The I/O circuit is configured to direct N pieces of data to or from N working banks in a corresponding second-level memory unit. The I/O control logic is configured to determine the N working banks from the N main banks and the redundant bank in the corresponding second-level memory unit based on bank fail information indicative of a failed main bank of the N main banks and control the I/O circuit to direct the N pieces of data to or from the N working banks, respectively.

Abstract: A circuit board, a display panel and a display apparatus are provided. The circuit board includes a main circuit board and an adapter circuit board stacked on the main circuit board. The adapter circuit board is provided with at least one first pad region, and the first pad region includes a hollowed region penetrating through the adapter circuit board and multiple first pads distributed around the hollowed region. The main circuit board is provided with at least one second pad region including multiple second pads, and the first pads of each of the first pad regions are respectively soldered to the multiple second pads of a corresponding second pad region.

Abstract: A method of peak power management (PPM) is provided for two NAND memory dies. Each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Abstract: A laminating device and a laminating method are disclosed. The laminating device is used for laminating a flexible panel together with a curved cover plate. The curved cover plate is provided with a central area and an edge bending area located in a first direction in the central area. The laminating device comprises a movable mechanism, which is arranged opposite the curved cover plate in a second direction and comprises: a first movable base table and a second movable base table, which are arranged opposite each other in the first direction; and an elastic supporting member, which is provided with an elastic supporting portion, the elastic supporting portion covering parts of the first movable base table station and the second movable base table station that are close to the curved cover plate, and being used for fixing the flexible panel.

Abstract: A display panel buffering structure, a display screen module and a preparing method therefor, and a terminal device are provided. The display panel buffering structure is arranged on the side face, facing away from a light-emitting side, of a display panel, and comprises: a buffering film provided with a hollow structure for accommodating an exciter; and a first light shielding film attached to a first side face, facing the display panel, of the buffering film. An orthographic projection of the first light shielding film on a plane where the first side face is located covers an orthographic projection of the hollow structure on the plane where the first side face is located, and a portion, opposite to the hollow structure, of the first light shielding film is fixed with the exciter.

Abstract: Methods for erasing storage data of a three-dimensional (3D) memory device are presented. The 3D memory device includes a plurality of memory blocks, each memory block having a plurality of memory strings with vertically stacked memory cells. Each memory cell is addressable through a word line and a bit line. The storage data in a selected memory block can be erased by applying an erase voltage on an array common source and applying a first voltage on the word lines of the selected memory block. Word lines of an unselected memory block are floating, i.e., without external bias, during the erasing operation. After the erasing operation, a second voltage is applied on the word lines of entire memory plane to reset the memory cells for improved data retention.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: A flexible printed circuit and a manufacturing method thereof, an electronic device module and an electronic device are provided. The flexible printed circuit includes a main sub-circuit board and a bridge sub-circuit board; the main sub-circuit board includes a first substrate, and a first bridge end, a second bridge end, a first wiring portion, and a second wiring portion on the first substrate; the bridge sub-circuit board includes a second substrate, and a third bridge end, a fourth bridge end, and a third wiring portion on the second substrate, the third bridge end and the fourth bridge end are electrically connected by the third wiring portion, and the bridge sub-circuit board is configured to be mounted on the main sub-circuit board by electrically connecting the third bridge end and the fourth bridge end to the first bridge end and the second bridge end, respectively.

Abstract: A method of peak power management (PPM) is provided for two NAND memory dies. Each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Abstract: A display apparatus includes a display panel, a touch layer, and a flexible printed circuit (FPC) including a main FPC and a bridge FPC. A third soldering region and a fourth soldering region of the bridge FPC are respectively soldered to a first soldering region and a second soldering region of the main FPC. Ends of each first touch connection line are electrically connected to a touch chip and a first touch lead. Ends of each second touch connection line are electrically connected to a pad on the second soldering region and a second touch lead. Ends of each third touch connection line are electrically connected to a pad on the first soldering region and the touch chip. Ends of each touch transfer line are electrically connected to a pad on the third soldering region and a pad on the fourth soldering region.

Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.

Abstract: A flexible printed circuit and a manufacture method thereof, an electronic device module and an electronic device are provided. The flexible printed circuit includes a main sub-circuit board and a transfer sub-circuit board. The main sub-circuit board includes a first transfer terminal, a first wiring portion and a second wiring portion; and the transfer sub-circuit board includes a second transfer terminal and a third wiring portion, and the third wiring portion electrically connects a first group of second contact pads with a second group of second contact pads of the second transfer terminal. The transfer sub-circuit board is configured to be mounted on the main sub-circuit board by electrically connecting the first group of second contact pads to the first group of first contact pads and electrically connecting the second group of second contact pads to the second group of first contact pads.

Abstract: An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

Abstract: Provided is a flexible display structure, including a reinforcing strip, and a flexible display panel and a supporting layer that are laminated. The flexible display panel is provided with a first surface and a second surface opposite to each other, and a first side surface connecting the first surface and the second surface, and the reinforcing strip is disposed on the first side surface and configured to adhere the flexible display panel to the supporting layer.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a display panel and a flexible circuit board electrically connected with the display panel. The flexible circuit board includes a first circuit board, a second circuit board and a conductive portion; the first circuit board includes a first substrate, and a main contact pad, a first wire and a second wire provided on the first substrate; the second circuit board includes a second substrate, a relay contact pad and a third wire provided on the second substrate; and the conductive portion is configured for electrically connecting the main contact pad and the relay contact pad.

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.