Patents by Inventor Rahul Jain

Rahul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11432405
    Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Prithwish Chatterjee, Kyu-oh Lee
  • Patent number: 11417614
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Publication number: 20220253848
    Abstract: An electronic payment transaction is subject to reversion. A payer can initiate payment by way of a first transaction that transfers an amount of money from a payer account to a payee account in near real time. Subsequently, the payer can issue a request to reverse the transaction due to error or fraud, for example. In response to the request, the first transaction can be reversed, for instance by a second transaction that transfers the amount of money from the payee account to the payer account. In accordance with one aspect, reversal can be permitted within a predetermined elapsed time from the first transaction. Further, checks performed prior to reversal can be employed to mitigate risk of fraud.
    Type: Application
    Filed: November 12, 2020
    Publication date: August 11, 2022
    Inventors: Suneela Tatineni, Naresh Golakoti, N. Rahul Jain
  • Publication number: 20220255896
    Abstract: Some embodiments provide a method for a managed forwarding element (MFE) executing on a data compute node (DCN) that operates on a host computer in a public datacenter. The MFE implements a logical network that connects multiple DCNs within the public datacenter. The method receives a packet, directed to the DCN, that (i) has a first logical network source address and (ii) is encapsulated with a second source address associated with an underlying public datacenter network. The method determines whether the first logical network source address is a valid source address for the packet based on a mapping table that maps logical network addresses to underlying public datacenter network addresses. When the first source address is not a valid source address for the packet, the method drops the packet.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Inventors: Rahul Jain, Mukesh Hira, Su Wang
  • Patent number: 11410921
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee
  • Publication number: 20220230951
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
  • Patent number: 11374794
    Abstract: Some embodiments provide a centralized overlay-network cloud gateway and a set of centralized services in a transit virtual cloud network (VCN) connected to multiple other compute VCNs hosting compute nodes (VMs, containers, etc.) that are part of (belong to) the overlay network. The centralized overlay-network cloud gateway provides connectivity between compute nodes of the overlay network (e.g., a logical network spanning multiple VCNs) and compute nodes in external networks. Some embodiments use the centralized overlay-network cloud gateway to provide transitive routing (e.g., routing through a transit VCN) in the absence of direct peering between source and destination VCNs. The overlay network, of some embodiments, uses the same subnetting and default gateway address for each compute node as the cloud provider network provided by the virtual private cloud provider.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 28, 2022
    Assignee: VMWARE, INC.
    Inventors: Mukesh Hira, Su Wang, Rahul Jain, Ganesan Chandrashekhar, Sandeep Siroya
  • Publication number: 20220188545
    Abstract: A method for enhancing the situational awareness of a user to a problem within an area. The method includes one or more computer receiving visual information corresponding to an area from a device associated with a user. The method further includes receiving data from a group of one or more sensors within the area, where the area includes a plurality of physical elements. The method further includes determining that a first problem is present within the area and a first physical element in the area that corresponds to the first problem, based on analyzing the data received from the group of sensors. The method further includes generating augmented reality (AR) content related to the first problem present within the area. The method further includes displaying, via the device associated with the user, the generated AR content related to the problem within the visual information corresponding to the area.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Inventors: Raghuveer Prasad Nagar, Sarbajit K. Rakshit, Manjit Singh Sodhi, Rahul Jain
  • Patent number: 11355459
    Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corpoation
    Inventors: Kyu-Oh Lee, Sai Vadlamani, Rahul Jain, Junnan Zhao, Ji Yong Park, Cheng Xu, Seo Young Kim
  • Patent number: 11349922
    Abstract: A database proxy includes a computing device and a hardware-accelerated database proxy module. The computing device includes one or more processors, memory, a first bus interface, and a network interface coupling the database proxy to one or more networks. The database proxy module includes a second bus interface coupled to the first bus interface via one or more buses, and a request processor. The database proxy is configured to receive a database read request from a client via the one or more networks and the network interface; forward the database read request to the request processor using the one or more buses; process, using the request processor, the database read request; and return results of the database read request to the client. In some embodiments, the computing device or the database proxy module further includes a flash memory interface for accessing one or more flash memory devices.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 31, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Chidamber Kulkarni, Amarnath Vishwakarma, Raushan Raj, Vijaya Raghava Chiyedu, Rahul Sachdev, Rahul Jain, Prasanna Sukumar, Prasanna Sundararajan
  • Patent number: 11343229
    Abstract: Some embodiments provide a method for a managed forwarding element (MFE) executing on a data compute node (DCN) that operates on a host computer in a public datacenter. The MFE implements a logical network that connects multiple DCNs within the public datacenter. The method receives a packet, directed to the DCN, that (i) has a first logical network source address and (ii) is encapsulated with a second source address associated with an underlying public datacenter network. The method determines whether the first logical network source address is a valid source address for the packet based on a mapping table that maps logical network addresses to underlying public datacenter network addresses. When the first source address is not a valid source address for the packet, the method drops the packet.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 24, 2022
    Assignee: VMWARE, INC.
    Inventors: Rahul Jain, Mukesh Hira, Su Wang
  • Patent number: 11336963
    Abstract: According to an embodiment of the present disclosure, a method comprises playing, by the media player, a 360-degree video. The method further comprises recording, by the media player, one or more viewing angles corresponding to a user's viewing of the 360-degree video. Further, the method comprises detecting, by the media player, a video seek event to a seek point of the 360-degree video. The method further comprises playing, by the media player, the 360-degree video from the seek point according to a viewing angle determined based on at least one of (a) a recorded viewing angle and (b) a view mode.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 17, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bhaskar Dutta, Manoj Verma, Rahul Jain
  • Patent number: 11335632
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
  • Patent number: 11330665
    Abstract: Various aspects include methods for Transmission Control Protocol (TCP)/Internet Protocol (IP) (TCP/IP) packet transmission and compression of headers for TCP/IP packet transmission. Various embodiments may include a packet data convergence protocol (PDCP) layer of a processing device applying least significant bit (LSB) encoding to a TCP Timestamp (TS) option of a TCP/IP packet using an offset parameter of zero to generate a compressed header in response to determining that a TCP TS field of the TCP/IP packet and a TCP TS field of a last TCP/IP packet transmitted have a same value. In some embodiments, a Timestamp Value (TSVal) field or a Timestamp Echo Reply (TSEcho) field of the TCP TS option of the compressed header may have a size of one byte.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 10, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Jain, Deepak Sah, Ganesh Babu Kamma
  • Publication number: 20220068847
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 3, 2022
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Publication number: 20220060375
    Abstract: A software upgrade to be deployed by a cloud extension agent is received by a remote network management platform, the cloud extension agent running locally on a network and initiating an outbound connection to the remote network management platform through a firewall of the network. A command is generated for the software upgrade, the command comprising an identification of a source of the software upgrade. The command is provided to the cloud extension agent, wherein providing the command causes the cloud extension agent to acquire the software upgrade from the identified source and deploy the software upgrade.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Inventors: Vineeth Narasimhan, Joshua Lambert, Thomas Herchek, Ryan Elliot Hope, Nitish Jha, Rahul Jain, Sumeet Singh
  • Patent number: 11256515
    Abstract: Techniques for accelerating compaction include compaction accelerator. The compaction accelerator includes a compactor separate from a processor performing read and write operations for a database or a data store. The compactor includes a plurality of compaction resources. The compactor is configured to receive a compaction request and data to be compacted, compact the data via a compaction pipeline to generate compacted data, and forward the compacted data to the processor, the database, or the data store. The compaction pipeline has a first portion of the plurality of compaction resources.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 22, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Chidamber Kulkarni, Rahul Jain, Prasanna Sundararajan
  • Publication number: 20220045879
    Abstract: A system and method for connecting virtual computer networks in a public cloud computing environment using a transit virtual computer network uses a cloud gateway device in the transit virtual computer network that includes a first-tier logical router and a plurality of second-tier logical routers connected to the virtual computer networks. A source Internet Protocol (IP) address of outgoing data packets from a particular virtual computer network is translated at a particular second-tier logical router of the cloud gateway device from an IP address of the particular virtual computer network to an internal IP address from a particular pool of IP addresses. The outgoing data packets are then routed to the first-tier logical router of the cloud gateway device, where the outgoing data packets are transmitted a destination network from a particular interface of the first-tier logical router of the cloud gateway device.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Rahul JAIN, Mukesh HIRA
  • Patent number: 11244912
    Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Kristof Kuwawi Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati, Telesphor Kamgaing
  • Publication number: 20220034060
    Abstract: The present disclosure envisages an anchor plate adapter. The anchor plate adapter comprises two or more type of locking interfaces to facilitate mounting of different chimneys. One or more first locking interfaces is configured on the adapter, wherein the first locking interface is configured as opposing holes on an inner wall and an outer wall. The chimney is securely mounted on and locked by means of one or more fasteners. Additionally, one or more second locking interfaces are configured in form of protrusions extending outward from the outer wall. The second locking interface engages with the inner protruding member configured on an abutting surface of the outer tube when the adapter is oriented in a position within a female interface of the chimney, and the female interface is rotated with respect to the adapter.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: Rajat Saxena, Peter M. Schmitz, Eric W. Palmbos, Michael R. Lutz, Rahul Jain