Patents by Inventor Rajeev Kumar

Rajeev Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11937114
    Abstract: A method of wireless communication includes determining, based on a plurality of network measurements performed by a user equipment (UE), one or more measurement log files associated with the plurality of network measurements. The method further includes receiving, by the UE from a network device, a request associated with the one or more measurement log files. The request indicates at least one measurement filter. The method further includes transmitting, by the UE to the network device, a response to the request. The response includes first measurement results of the one or more measurement log files selected based on the at least one measurement filter and excludes second measurement results of the one or more measurement log files based on the at least one measurement filter.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 19, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Rajeev Kumar, Xipeng Zhu, Shankar Krishnan, Ozcan Ozturk, Masato Kitazoe, Gavin Bernard Horn
  • Publication number: 20240089234
    Abstract: Automated techniques for converting network devices from a Layer 2 (L2) network into a Layer 3 (L3) network in a hierarchical manner are described herein. The network devices may be configured to boot such that their ports are in an initialization mode in which the ports are unable to transmit locally generated DHCP packets. When a network device detects that a neighbor (or “peer”) device has acquired an IP address or has been configured by a network controller, then the port on which the neighbor device is detected can then be transitioned from the initialization mode into a forwarding mode. In the forwarding mode, the port can be used to transmit packets to obtain an IP address. Thus, the network devices are converted from an L2 device to an L3 device in a hierarchical order such that upstream devices are discovered and converted into L3 devices before downstream devices.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Rajeev Kumar, Sanjay Kumar Hooda, Ramesh Chandra Yeevani-Srinivas
  • Publication number: 20240089761
    Abstract: Methods, systems, and devices for wireless communication are described in which an access point (AP) may advertise Internet connection quality information in a beacon transmission or probe request. The AP may measure one or more metrics associated with Internet access, and provide an indication of the metrics in an information element transmitted to one or more stations (STAs). In some examples, an Internet connection quality information element may include one or more fields associated with connection metrics, such as Internet reachability, link latency, available uplink bandwidth, and available downlink bandwidth. STAs may look for the Internet connection quality information element and may decide whether to connect to an AP based on the indicated metrics.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventor: Rajeev Kumar
  • Patent number: 11923848
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 5, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11924770
    Abstract: A UE may calculate an allocation of a transmission power for a first uplink transmission on a first uplink channel and at least one second uplink transmission on at least one second uplink channel, the transmission power being allocated in each symbol of a plurality of symbols in a slot. The UE may detect a transmission power change in the allocation of the transmission power in the slot for at least one of the first uplink transmission or the at least one second uplink transmission. The UE may determine whether to adjust the allocation of the transmission power for the at least one of the first uplink transmission or the at least one second uplink transmission to eliminate the transmission power change in the slot for the at least one of the first uplink transmission or the at least one second uplink transmission.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Brahim Saadi, Dinesh Kumar Devineni, Rajeev Malasani, Anoop Ramakrishna, Ruhua He, Enoch Shiao-Kuang Lu, Raghu Narayan Challa
  • Patent number: 11922105
    Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 5, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
  • Publication number: 20240067882
    Abstract: A system for stabilizing a hydrocarbon feedstock includes a High Pressure Separation (HPS) unit in fluid communication with a feedstock inlet. The HPS unit includes an oil outlet. A Heated Low Pressure (LP) Separator unit is downstream from the oil outlet of the HPS unit. The Heated LP Separator unit includes an oil outlet.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 29, 2024
    Applicant: T.EN Process Technology Inc.
    Inventors: Rajeev Nanda, Praveen Kumar, Cong Dinh
  • Publication number: 20240060351
    Abstract: An apparatus can include a door control mechanism that defines a cavity. The door control mechanism can include an actuator body comprising a contact surface. The door control mechanism can include a projection that extends from the actuator body into the cavity. The apparatus can include a spacer to be disposed in the cavity. The spacer can include a spacer body, a first stopper, and a second stopper. The first stopper can extend from the spacer body. The first stopper can interface with the contact surface of the actuator body. The second stopper can extend from a surface of the spacer body. The second stopper can interface with the projection of the door control mechanism. At least one of the first stopper and the second stopper can prevent the door control mechanism from actuating in response to a manual force.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Rajeev Kumar Singh, Marcus Merideth
  • Publication number: 20240064550
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may start a timer for obtaining quality of experience (QoE) measurements. The UE may obtain the QoE measurements until the timer expires. The UE may transmit information indicating the QoE measurements. Numerous other aspects are described.
    Type: Application
    Filed: April 1, 2021
    Publication date: February 22, 2024
    Inventors: Jianhua LIU, Xipeng ZHU, Shankar KRISHNAN, Rajeev KUMAR, Charles Nung LO, Juan ZHANG
  • Publication number: 20240064574
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit, to a network node, UE capability information associated with at least one machine learning component. The UE may receive, from the network node and based on the UE capability information, configuration information corresponding to the at least one machine learning component. The UE may generate a first machine learning output based on the machine learning component. The UE may perform a communication task based on the first machine learning output. Numerous other aspects are described.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Rajeev KUMAR, Aziz GHOLMIEH, Gavin Bernard HORN, Xipeng ZHU
  • Publication number: 20240064065
    Abstract: Example implementations include a method, apparatus and computer-readable medium of wireless communication by a user equipment (UE), comprising receiving parameter set configuration information from a network entity, the parameter set configuration information corresponding to a model structure employed in a machine learning operation by the UE for the wireless communication. The implementations further include activating a parameter set in response to an activation condition, the parameter set identified within the parameter set configuration information as being associated with the activation condition.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Rajeev KUMAR, Xipeng Zhu, Gavin Bernard Horn, Aziz Gholmieh
  • Patent number: 11910618
    Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: February 20, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
  • Patent number: 11909391
    Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 20, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11908704
    Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 20, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, Fnu Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
  • Publication number: 20240054357
    Abstract: Certain aspects of the present disclosure provide techniques for wireless communications by a user equipment (UE). The UE receives a configuration for at least one machine learning function name (MLFN). The UE receives machine learning (ML) data associated with the at least one MLFN. The UE uses the ML data as an input for at least one of: operation or training of an ML model associated with the at least one MLFN.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Inventors: Rajeev KUMAR, Gavin Bernard HORN, Xipeng ZHU, Shankar KRISHNAN, Aziz GHOLMIEH
  • Publication number: 20240056798
    Abstract: Aspects described herein relate to receiving, from a network node, a list of supported models or model structures (MS) identifiers (IDs) per machine learning function name (MLFN) or machine learning feature (MLF) at the network node, updating a capability at the UE to an updated capability based on the list of supported models or MS IDs per MLFN or MLF at the network node, and downloading, at the UE and from a model repository, one or more models or MSs per MLFN or MLF based on the updated capability and available resources at the UE. Other aspects relate to transmitting the list of supported models or MS IDs and configuring use of a model or MS ID for a particular MLFN or MLF.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Inventors: Rajeev KUMAR, Gavin Bernard HORN, Xipeng ZHU, Aziz GHOLMIEH
  • Patent number: 11901891
    Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 13, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11899613
    Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 13, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11903219
    Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: February 13, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
  • Patent number: 11902166
    Abstract: Routing of a traffic in a fabric network may be provided. A first traffic may be received at a first node. It may be determined that the first traffic is coming from a provider virtual network. In response to determining that the first traffic is coming from the provider virtual network, it may be determined that a first subnet associated with the first traffic is associated with a subscriber virtual network. In response to determining that the first subnet associated with the first traffic is associated with the subscriber virtual network, a first virtual network associated with the first traffic may be changed to the subscriber virtual network. A lookup for the first traffic may be changed to a first virtual routing and forwarding of the subscriber virtual network.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 13, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Raja Janardanan, Rajeev Kumar, Sanjay Kumar Hooda, Prakash C. Jain