Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may transmit, to a network entity, a consent profile registration request, the consent profile registration request identifying a user identifier. The UE may transmit, to the network entity, a consent profile based at least in part on the consent profile registration request, the consent profile comprising one or more consent types for the user identifier that configure one or more consent parameters for the user identifier on a least a per-user basis.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive a message from a network entity indicating a set of machine learning models, a set of parameter sets, or both and one or more usage conditions associated with the machine learning models and parameter sets. Based on a usage condition being satisfied, the UE may select a machine learning model, a parameter set, or both for generating a machine learning inference. For example, the UE may select the machine learning model or the parameter set based on a priority, whether sufficient input data is provided, or based on other usage conditions. The UE may generate the machine learning inference using the selected machine learning model or the selected parameter set, and the UE may transmit a report indicating an output of the machine learning inference to the network entity.

Abstract: A source network node and a UE may obtain at least one mobility related prediction associated with the UE or at least one target network node, the at least one mobility related prediction being derived by at least one neural network, and the source network node may handover the UE from the source network node to the at least one target network node based on the at least one mobility related prediction. The target network node may receive the handover request, obtain at least one mobility related prediction associated with the UE or the target network node, and output for transmission a handover request ACK, the handover request ACK based at least in part on the at least one mobility related prediction.

Abstract: Methods, systems, and devices for wireless communications are described. Some user equipment (UE) may be equipped with multiple subscriber identity modules (SIMs). A multi-SIM UE may receive a control message at a first SIM which indicates a set of sounding reference signal (SRS) resources for receiving SRS according to a first periodicity. The UE may also receive a registration message at a second SIM which includes a first parameter indicating a first set of paging occasions for receiving paging messages in accordance with a second periodicity. The UE may identify a collision in time between the one or more SRS resources and paging resources, and may transmit a registration request message to a base station. The UE may then receive a second registration message which includes a second parameter for calculating a second set of paging occasions that have a third periodicity that are non-overlapping with the SRS resources.

Abstract: A device in a wireless network may process information with machine learning associated with a model ID, a machine learning function, or a machine learning use case and report data via the wireless communication based on a configuration associated with the model ID, the machine learning function, or the machine learning use case. A device may provide a configuration for machine learning associated with a model ID, a machine learning function or, a machine learning use case; and may receive a report of data based on the configuration associated with the model ID, the machine learning function, or the machine learning use case.

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine one or more candidate base stations for a handover procedure for the UE. The UE may transmit an indication of the one or more candidate base stations to a serving base station. Numerous other aspects are provided.

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

Abstract: Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a first network node in a radio access network (RAN) may transmit mobility history data for a user equipment (UE) to a second network node in a core network associated with the RAN. The first network node may receive a UE mobility prediction model that is based at least in part on the mobility history data from the second network node. Numerous other aspects are described.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a UE capability for AI/ML. A UE may receive a request from a network to report a UE capability for at least one of an AI procedure or an ML procedure. The UE may transmit to the network, based on the request to report the UE capability, an indication of one or more of an AI capability, an ML capability, a radio capability associated with the at least one of the AI procedure or the ML procedure, or a core network capability associated with the at least one of the AI procedure or the ML procedure.

Abstract: In one embodiment, network node-to-node connectivity verification is performed in a network including data path processing of packets within a packet switching device. In one embodiment, an echo request connectivity test packet, emulating an echo request connectivity test packet received from a first connected network node, is inserted by the packet switching device prior in its data processing path prior to ingress processing performed for packets received from the first connected network node. A correspondingly received echo reply connectivity test packet is intercepted by the packet switching device during data path egress processing performed for packets to be forwarded to the first connected network node.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.