Abstract: Methods, devices, and mechanisms for detecting and reporting successful secondary node and/or primary secondary cell group cell (PScell) changes are provided. In one example, a method of wireless communication performed by a first network unit comprises: transmitting, to a second network unit, an indication of a primary secondary cell group cell (PScell) change associated with a user equipment (UE); transmitting, based on the indication, a SPC configuration; and receiving a SPC report, wherein the SPC report is based on the SPC configuration and SPC information associated with the UE.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: A user equipment (UE) disconnects from next generation radio access network (NG-RAN) base station (BS) and receives, from the NG-RAN BS, a fallback indication. The UE then attempts to connect to an evolved-universal mobile telecommunications system terrestrial radio access network (E-UTRAN) BS. The UE determines that communication with the E-UTRAN BS was not established and identifies an alternate BS. After establishing communication with the alternate BS, the UE generates and transmits a report to the alternate BS including the fallback indication and information relating to the failed connection attempt with the E-UTRAN BS. The report is then conveyed to the NG-RAN BS for optimization of future fallback procedures.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: Methods, systems, and devices for wireless communication are described. A first wireless device may establish a communication session with a second wireless device using a neighbor awareness networking (NAN) radio access technology (RAT). The first wireless device may transmit a first indication that the first wireless device is capable of using a secured ranging protocol. The first wireless device may receive a second indication that the second wireless device is also capable of using the secured ranging protocol. The first wireless device may determine one or more setup parameters to use for a ranging procedure between the first wireless device and the second wireless device based on the first indication and the second indication. Accordingly, the first wireless device may obtain a measurement report after using the secured ranging protocol to perform the ranging procedure in accordance with the one or more setup parameters.

Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: A computer-implemented system provides a chatbot communications network between a plurality of system participating users including merchants and clients. The system comprises a system controller with a memory. A user device communicates with the system controller and comprises an input/output interface for inputting commands to the system controller and for outputting information from the system controller. The system controller creates at least one chatbot framework for a responding user such as a merchant. User content is converted in real time content into converted chatbot content within the chatbot framework. A chatbot interface is created to be communicated to initiating users such as clients via the input/output interface. Initiator users such as clients input queries and/or commands from their user device related to responding user content such as merchant content via the user chatbot interface.

Abstract: A method for modulating a position of a movable command input image displayed on a graphical user interface (GUI) based on a user viewing direction relative to graphical user interface comprises capturing real time images of the user's face, eyes and irises. The general eye orientation of the user is determined based on the real time images. A first position of the movable command input image displayed on the GUI is determined. The GUI is separated into portions. A real-time correlation between the general eye orientation and one or more of the interface portions is determined thereby determining a viewing direction of the user and one or more real-time viewed interface portions. The movable command input image is moved from the first position to a second position on the GUI. The second position is at the one or more real-time viewed interface portions.

Abstract: Embodiments provide methods, and server systems for enhancing checkout experience of an e-commerce transaction. A method includes receiving, by a server system associated with a payment network, a pre-authentication request signal for a prospective e-commerce transaction for a payment card of user. The pre-authentication request signal includes a time data for an expected transaction time, a transaction amount data, a payment card data and at least one transaction identifier data. The method includes electronically facilitating a pre-authentication of the prospective e-commerce transaction based at least on performing a multi-factor pre-authentication. Upon successful pre-authentication, the method includes storing a pre-authenticated transaction data. The method includes sending a notification signal of successful pre-authentication to a user device.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) associated with a first subscription and a second subscription may establish a connection with a base station, the first subscription in a connected state. The UE may use the first subscription to perform a communication activity with the base station while the first subscription is in the connected state. Upon completion of the communication activity, the UE may transmit UE assistance information (UAI) to the base station indicating a preference of the UE to switch the first subscription to an inactive state in response to a release message from the base station.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.

Abstract: Methods, systems, and devices for wireless communications are described. A communication link between the UE and a serving base station may be established. The UE may measure, at an application layer of the UE, a set of quality of experience variables associated with different service types. The UE may measure, at an access stratum of the UE, a set of radio resource management variables associated with the communication link between the UE and the serving base station and a communication link between the UE and a corresponding set of one or more neighboring base stations associated with the communication links. The UE may transmit a measurement report to the serving base station indicating information associated with the quality of experience variables and the radio resource management variables in a multi-layer readable format.

Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.

Abstract: Automated techniques for converting network devices from a Layer 2 (L2) network into a Layer 3 (L3) network in a hierarchical manner are described herein. The network devices may be configured to boot such that their ports are in an initialization mode in which the ports are unable to transmit locally generated DHCP packets. When a network device detects that a neighbor (or “peer”) device has acquired an IP address or has been configured by a network controller, then the port on which the neighbor device is detected can then be transitioned from the initialization mode into a forwarding mode. In the forwarding mode, the port can be used to transmit packets to obtain an IP address. Thus, the network devices are converted from an L2 device to an L3 device in a hierarchical order such that upstream devices are discovered and converted into L3 devices before downstream devices.