Abstract: A method and apparatus for a CTC data copy operation, in that modification, and subsequent encoding only affects a small portion of metadata associated with copied data. By modifying and re-encoding only this small portion of metadata, a small portion of the parity data for the copied data requires updating. In embodiments where there are no errors in the read data to be copied (e.g., from an SLC portion of a NAND), decoding, modification, and encoding, may be done in parallel. Because such a small number of metadata bits are modified, in some embodiments, all possible codewords for the parity bits may be predetermined and combined (e.g., by XOR) to update the metadata parity bits.

Abstract: A decoding system and method of a non-volatile memory are provided in which information regarding a characteristic of a non-volatile memory is used to determine an initial log-likelihood-ratio (LLR) table from among a number of LLR tables. The decoding is then performed using the determined initial LLR table.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: A storage system has a controller with an encoder. The encoder is configured to perform first and second stages of an encoding process in parallel on pipelined data blocks. In this way, while the first stage of the encoding process is being performed on a first data block, the second stage of the encoding process is performed on a second data block.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.

Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.

Abstract: Technology for recovering data in memory dies is disclosed. A set of codewords may be stored across a set of memory dies. One of the memory dies stores redundancy information that is based on information from each codeword in the set of codewords. Each of the memory dies is bonded to control die through bond pads that allow communication between the control die and the memory die. If decoding of one of more codewords fails, the redundancy information may be used to recover data bits of all the codewords in the set. The redundancy information may be sent to a memory controller that is in communication with the control dies, which performs the data recovery.

Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Abstract: Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Abstract: An illustrative embodiment of this disclosure is an apparatus, including a memory, a processor in communication with the memory, and a decoder. The processor is configured to train a classifier, calculate one or more features of a codeword, predict an outcome of decoding the codeword with the decoder, and determine, using the classifier, whether the outcome satisfies a predetermined threshold. In some embodiments, based on the outcome, the processor selects a set of decoder parameters to improve decoder performance.

Abstract: A data storage system performs operations including receiving a data write command specifying data to be written; selecting an irregular LDPC encoding scheme of a plurality of available irregular LDPC encoding schemes available to the encoder in accordance with (i) a working mode of the data storage system, (ii) device-specific criteria and/or (iii) a data type of the specified data; and encoding the specified data to be written using the selected irregular LDPC encoding scheme.

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Abstract: A data storage system performs operations including receiving a data write command specifying data to be written; selecting an irregular LDPC encoding scheme of a plurality of available irregular LDPC encoding schemes available to the encoder in accordance with (i) a working mode of the data storage system, (ii) device-specific criteria and/or (iii) a data type of the specified data; and encoding the specified data to be written using the selected irregular LDPC encoding scheme.

Abstract: A storage device may include a decoder configured to connect bits to a content node based on content-aware decoding process. The content-aware decoding process may be dynamic and determine connection structures of bits and content nodes based on patterns in data. In some cases, the decoder may connect non-adjacent bits to a content node based on a content-aware decoding process. In other cases, the decoder may connect a first number of bits to a first content node and a second number of bits to a second content node. In such cases, the first number of bits and the second number of bits are a different number.

Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

Abstract: Technology is described herein for a generalized low-density parity-check (GLDPC) decoder. A GLDPC decoder comprises an LDPC decoder and a syndrome decoder. The LDPC decoder is configured to generate a codeword for encoded data. The syndrome decoder is configured to decode a syndrome of punctured check nodes based on a linear block code having more than one information bit. The GLDPC decoder is configured to control the LDPC decoder to compute an initial value of the syndrome of the punctured check nodes based on an initial estimate of the codeword from the LDPC decoder. The GLDPC decoder is configured to alternate between controlling the syndrome decoder to correct the syndrome and controlling the LDPC decoder to update the codeword based on the corrected syndrome. The GLDPC decoder is configured to provide a decoded version of the encoded data based on a final estimate of the codeword.