Abstract: A storage device may include a decoder configured to connect bits to a content node based on content-aware decoding process. The content-aware decoding process may be dynamic and determine connection structures of bits and content nodes based on patterns in data. In some cases, the decoder may connect non-adjacent bits to a content node based on a content-aware decoding process. In other cases, the decoder may connect a first number of bits to a first content node and a second number of bits to a second content node. In such cases, the first number of bits and the second number of bits are a different number.

Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

Abstract: Technology is described herein for a generalized low-density parity-check (GLDPC) decoder. A GLDPC decoder comprises an LDPC decoder and a syndrome decoder. The LDPC decoder is configured to generate a codeword for encoded data. The syndrome decoder is configured to decode a syndrome of punctured check nodes based on a linear block code having more than one information bit. The GLDPC decoder is configured to control the LDPC decoder to compute an initial value of the syndrome of the punctured check nodes based on an initial estimate of the codeword from the LDPC decoder. The GLDPC decoder is configured to alternate between controlling the syndrome decoder to correct the syndrome and controlling the LDPC decoder to update the codeword based on the corrected syndrome. The GLDPC decoder is configured to provide a decoded version of the encoded data based on a final estimate of the codeword.

Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

Abstract: A controller may detect unreliable bits of data, memory cells, or bit lines during an error correction process of a read operation based on an error correction code used to generate parity bits for the data. In some embodiments, the controller may use the error correction code to determine a distribution of unsatisfied checks. Based on the distribution, the controller may detect group(s) of bits that more closely resemble a defective group of bits rather than a non-defective group of bits. Based on the detection, the controller may set reliability metrics to values that indicate low levels or reliability, which in turn may increase the probability of successfully correcting the errors and reduce the amount of work the controller needs to do in order to complete the error correction process.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Abstract: Technology is described herein for a generalized low-density parity-check (GLDPC) decoder. A GLDPC decoder comprises an LDPC decoder and a syndrome decoder. The LDPC decoder is configured to generate a codeword for encoded data. The syndrome decoder is configured to decode a syndrome of punctured check nodes based on a linear block code having more than one information bit. The GLDPC decoder is configured to control the LDPC decoder to compute an initial value of the syndrome of the punctured check nodes based on an initial estimate of the codeword from the LDPC decoder. The GLDPC decoder is configured to alternate between controlling the syndrome decoder to correct the syndrome and controlling the LDPC decoder to update the codeword based on the corrected syndrome. The GLDPC decoder is configured to provide a decoded version of the encoded data based on a final estimate of the codeword.

Abstract: A storage device may include a decoder configured to connect bits to a content node based on content-aware decoding process. The content-aware decoding process may be dynamic and determine connection structures of bits and content nodes based on patterns in data. In some cases, the decoder may connect non-adjacent bits to a content node based on a content-aware decoding process. In other cases, the decoder may connect a first number of bits to a first content node and a second number of bits to a second content node. In such cases, the first number of bits and the second number of bits are a different number.

Abstract: An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.

Abstract: A controller may detect unreliable bits of data, memory cells, or bit lines during an error correction process of a read operation based on an error correction code used to generate parity bits for the data. In some embodiments, the controller may use the error correction code to determine a distribution of unsatisfied checks. Based on the distribution, the controller may detect group(s) of bits that more closely resemble a defective group of bits rather than a non-defective group of bits. Based on the detection, the controller may set reliability metrics to values that indicate low levels or reliability, which in turn may increase the probability of successfully correcting the errors and reduce the amount of work the controller needs to do in order to complete the error correction process.

Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

Abstract: Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.

Abstract: A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: An apparatus includes a first single-port memory, a second single-port memory, and one or more control circuits in communication with the first single-port memory and in communication with the second single-port memory. The one or more control circuits are configured to initiate a read of stored data on a clock cycle from a physical location of the stored data in the first or second single-port memory and to initiate a write of fresh data on the clock cycle to whichever of the first single-port memory or the second single-port memory does not contain the physical location of the stored data.

Abstract: Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.