Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.

Abstract: A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit.

Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

Abstract: A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory, a selector and a time domain transformer. The selector is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.