Abstract: Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.

Abstract: A memory chip stack is described. The memory chip stack includes memory chips having a first plurality of memory channels, where non-yielding ones of the memory channels are to be disabled during operation of the memory chip stack. The first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack.

Abstract: Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

Abstract: A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

Abstract: A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

Abstract: A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

Abstract: A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

Abstract: An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits reside on a second die. The receiver circuits have no termination and no equalization. The second die has a slave device responsive to the master device of the first die. Conductive lines connect the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched.

Abstract: Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.

Abstract: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Abstract: Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.