Abstract: A device is presented including a a first hub. A bus is connected to the first hub. A second hub is connected to the bus. The first hub forms and transmits streaming packets including one packet header. Also presented is a system including a processor. A memory is connected to the processor. A first hub is connected to the processor. A second hub is connected to the first hub. Many peripheral components are connected to the second hub. The first hub forms and transmits streaming packets including one packet header.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A method and apparatus for the optimization of memory read operations via a sideband read return header are disclosed. A read request is received initiating a read, and a read return header is sent in advance of sending the read results.

Abstract: A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

Abstract: A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Abstract: Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.

Abstract: A volume rendering processor renders a two-dimensional image from a volume data set of voxels constituting a three-dimensional representation of an object. Voxel memory interface logic retrieves the voxels from a voxel memory in a scanned order with respect to X, Y and Z coordinate axes, the Z axis being the axis most nearly parallel to a predefined viewing direction. The set of voxels having equal Z coordinate values are referred to as a “slice” of voxels. Interpolation logic calculates a sequence of samples from the retrieved voxels such that (i) each sample lies along a corresponding imaginary ray extending through the object parallel to the viewing direction, (ii) each sample results from interpolating the eight voxels surrounding the sample in the XYZ coordinate system. “Supersampling” in the Z dimension is performed such that the number of samples calculated for each ray is greater than the number of slices of voxels in the volume data set.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: According to one embodiment, a computer system comprises a central processing unit (CPU), a memory control hub (MCH) coupled to the CPU, a point to point interface coupled to the MCH; and an input/output control hub (ICH) coupled to the point to point interface. The MCH delays arbitration of a request to access the point to point interface until the access request is received at the ICH, and ICH delays arbitration of a request to access the point to point interface until the access request is received at the MCH.

Abstract: A volume rendering processor renders a two-dimensional image from a volume data set of voxels constituting a three-dimensional representation of an object. Voxel memory interface logic retrieves the voxels from a voxel memory in a scanned order with respect to X, Y and Z coordinate axes, the Z axis being the axis most nearly parallel to a predefined viewing direction. The set of voxels having equal Z coordinate values are referred to as a “slice” of voxels. Interpolation logic calculates a sequence of samples from the retrieved voxels such that (i) each sample lies along a corresponding imaginary ray extending through the object parallel to the viewing direction, (ii) each sample results from interpolating the eight voxels surrounding the sample in the XYZ coordinate system. “Supersampling” in the Z dimension is performed such that the number of samples calculated for each ray is greater than the number of slices of voxels in the volume data set.

Abstract: A method renders a volume data set including a plurality of voxels. In the method, a). the volume data set is apportioned into a plurality of sections. Then, b). a first one of the plurality of sections is rendered by sequentially reading groups of voxels from an external memory and rendering the groups of voxels in the section. Then, c). any accumulated data from the rendering of the first one of the plurality of sections is stored in a temporary storage device. Then, a next one of the plurality of sections is rendered by sequentially reading groups of voxels of the next one of the plurality of sections from an external memory and rendering the groups of voxels, the rendering incorporating accumulated data from the temporary storage device, and then any accumulated data from the rendering of the next one of the plurality of sections is stored in the temporary storage device. Steps d and e are repeated until each of the plurality of sections of the volume data set have been rendered.

Abstract: An apparatus renders a volume data set including a plurality of voxels stored in a voxel memory. The apparatus includes a plurality of pipelines operating in parallel. Each pipeline includes a buffer storing at least one block of at least two voxels of the volume data set. An interpolation stage reads the at least one block of at least two voxels from the buffer. A gradient estimation stage receives an output from the interpolation stage. A compositing stage receives an output from the gradient estimation stage. The apparatus also includes a plurality of interface devices, wherein each interface device couples a particular stage only to an adjacent identical stage in a neighboring pipeline so that identical stages of the pipelines are connected in a ring.

Abstract: A volume graphics device renders a volume data set. The volume data set is apportioned into blocks of volume data, and each of the blocks are apportioned into a plurality of mini-blocks, each mini-block includes at least two voxels of volume data. The volume graphics device includes memory apportioned into a plurality of portions, wherein neighboring blocks of the volume data set are each stored in different ones of the plurality of portions of the memory, and wherein the mini-blocks of each block are stored in consecutive locations in the portion of memory associated with the associated block.

Abstract: A network interface for a connection-based communication network has support for message processing, including an interface for communication with an optional message coprocessor that performs a variety of message processing operations. Message processing is low level processing of messages between the host computer and the network. Such processing is performed on transmission in response to control information provided by the host and is performed on reception in response to control information included in incoming messages. Message processing includes low latency remote read and remote write operations, message filtering, and message demultiplexing. Such a network interface provides support for a variety of message processing operations using the coprocessor, while the complexity and cost of the network interface due to this support is minimal. The network interface provides control information for a message to the message coprocessor.

Abstract: A network interface is used to connect a host computer to a network to allow application programs running on the host computer to access the network. Each application program has a set of queues for handling transmit and receive requests. A network interface having direct application access channels has a set of physical registers for storing a set of pointers to one or more of these queues. The set of registers is multiplexed among several ring queues to provide virtual direct application access channels. Such multiplexing is performed by storing the pointers for each queue in memory, e.g., a local memory of the network interface or memory of the host computer. When a transmit or receive request for a given application is processed by the network interface, the network interface determines which set of pointers to use for a queue for the application and loads the correct set of pointers for the queue from the memory and into the set of registers.

Abstract: Apparatus is provided to enable real-time volume rendering on a personal computer or a desktop computer in which a technique involving blocking of voxel data organizes the data so that all voxels within a block are stored at consecutive memory addresses within a single memory model, making possible fetching an entire block of data in a burst rather than one voxel at a time. This permits utilization of DRAM memory modules which provide high capacity and low cost with substantial space savings. Additional techniques including sectioning reduces the amount of intermediate storage in a processing pipeline to an acceptable level for semiconductor implementation. A multiplexing technique takes advantage of blocking to reduce the amount of data needed to be transmitted per block, thus reducing the number of pins and the rates at which data must be transmitted across the pins connecting adjacent processing modules with each other.

Abstract: A network interface for a connection-based communication network has support for remote operations with reply, such as a remote read operation, that bypass host computer interaction. Such a network interface has support for general message processing operations which bypass host processor involvement. Message processing is low level processing of message between the host computer and the network. Such processing is performed on transmission in response to control information provided by the host and is performed on reception in response to control information included in incoming messages. Message processing includes low latency remote read and remote write operations, message filtering, and message demultiplexing. Such a network interface handles incoming messages containing destination control information indicating an operation to be performed, and possibly one or more operands.

Abstract: A network protocol and interface using direct deposit messaging provides low overhead communication in a network of multi-user computers. This system uses both sender-provided and receiver-provided information to process received messages and to deposit data directly in memory and to conditionally interrupt a host processor based on control information. Message processing is separated into data delivery, which bypasses the host processor and operating system, and message actions which may or may not require host processor interaction. In this protocol, a message includes an indication of the operation desired by the sender, an operand specified by the sender and an operand which refers to some information stored at the receiver. The receiver ensures that the desired action is permitted and then, if the action is permitted, performs the action according to both the operand specified by the sender and the state of the receiver.