Abstract: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

Abstract: An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a cache memory coupled to a processor. The apparatus additionally includes a tag storage structure that is coupled to the cache memory. The tag storage structure can store a tag associated with a location in the cache memory. The apparatus additionally includes a cache of cache tags coupled to the processor. The cache of cache tags can store a smaller subset of the tags stored in the tag storage structure.

Abstract: Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same rank, bank and page; select and transmit write commands from one chain at a time until each chain is done; and select a next chain of write commands to transmit, while creating and using a write page closing hint to determine when a change between pages of a given rank and bank should bring about the preemptive closing of a page to minimize incidents of incurring lengthy page miss delays.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Abstract: Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

Abstract: In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only provide signals, and the control circuitry is to control whether the third ports are to only receive signals or only provide signals. Other embodiments are described and claimed.

Abstract: Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.

Abstract: Apparatus and method to select write transactions and to selectively mark a write transaction with a page closing hint to cause the page in a memory device to which the write transaction is directed to be closed immediately after the write transaction is carried out if no other write transaction is found in a buffer of pending write transactions that is directed to the same rank, bank and page to minimize incidents of incurring lengthy page miss delays.

Abstract: Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

Abstract: A device is presented including a a first hub. A bus is connected to the first hub. A second hub is connected to the bus. The first hub forms and transmits streaming packets including one packet header. Also presented is a system including a processor. A memory is connected to the processor. A first hub is connected to the processor. A second hub is connected to the first hub. Many peripheral components are connected to the second hub. The first hub forms and transmits streaming packets including one packet header.

Abstract: A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

Abstract: A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.

Abstract: A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a read request pending for transmission over the half-duplex bus. A second agent then samples the preempt signal sent by the first agent. The second agent relinquishes ownership of the half-duplex bus responsive to the preempt signal to allow the read request to be sent across the half-duplex bus.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first agent, a point to point half duplex interface coupled to the first agent and a second agent coupled to the first point to point half duplex interface. The first agent is adaptable to transmit a signal to the second agent via a first component of the interface indicating the type of data traffic to be transmitted to the second agent.

Abstract: Prefetching data includes issuing a first request to prefetch data from a memory, receiving a response to the first request from the memory, obtaining a measure of latency between the first request and the response, and controlling issuance of a subsequent request to prefetch other data from the memory based on the measure.

Abstract: A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.

Abstract: A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.