Patents by Inventor Robert A. May

Robert A. May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11909826
    Abstract: Various embodiments provide systems and methods for automatically defining and enforcing network sessions based upon at least four dimensions of segmentation.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 11908821
    Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
  • Patent number: 11908802
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Patent number: 11885610
    Abstract: A method for determining the thickness of a plurality of coating layers. The method comprises the steps of performing a calibration analysis on calibration data to determine initial values and search limits of optical parameters of the plurality of coating layers, irradiating the plurality of layers with a pulse of THz radiation in the range from 0.01 THz to 10 THz, detecting the reflected radiation to produce a sample response derived from the reflected radiation, producing a synthesized waveform using the optical parameters and predetermined initial thicknesses of the layers, varying the thicknesses and the optical parameters within the search limits to minimize the error measured between the sample response and the synthesized waveform, and outputting the thicknesses of the layers.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 30, 2024
    Assignee: TeraView Limited
    Inventors: Ian Stephen Gregory, Robert May, Daniel James Farrell
  • Publication number: 20240006327
    Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Robert A. May, Brandon Marin, Benjamin Duong, Suddhasattwa Nad, Hsin-Wei Wang, Leonel Arana, Darko Grujicic
  • Publication number: 20240007438
    Abstract: Systems, devices, and methods are discussed for treating a number of network security devices in a cooperative security fabric using a cloud based root.
    Type: Application
    Filed: July 4, 2022
    Publication date: January 4, 2024
    Applicant: Fortinet, Inc.
    Inventor: Robert A. May
  • Patent number: 11862552
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Patent number: 11854834
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20230387782
    Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 30, 2023
    Inventors: Michael Robert May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick Johannus De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamas Marozsak, Andras V. Horvath
  • Publication number: 20230383813
    Abstract: The auxiliary suspension device is relatively neutral at rest and responds in coordination with the existing suspension system upon application of a load. The redundant suspension device has an inflatable bellow that is mounted between a vehicle's frame and an existing vehicle suspension element.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: RB Distribution, Inc.
    Inventors: Tam Van Nguyen, Matthew Robert May, Sean Cattie, Bryan McMasters, David Cimbolo
  • Publication number: 20230326866
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 12, 2023
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Publication number: 20230328105
    Abstract: Systems, devices, and methods are discussed for treating a number of network security devices in a cooperative security fabric as a unified object for configuration purposes.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 12, 2023
    Applicant: Fortinel, Inc.
    Inventors: Michael Xie, Robert A. May, Lino Xu, Jordan E. Thompson
  • Publication number: 20230308090
    Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.
    Type: Application
    Filed: March 27, 2023
    Publication date: September 28, 2023
    Inventors: Peter Onody, Tamas Marozsak, Michael Robert May, Fernando Naim Lavalle Aviles, Patrick Johannus De Bakker
  • Patent number: 11770403
    Abstract: Systems and methods for a security rating framework that translates compliance requirements to corresponding desired technical configurations to facilitate generation of security ratings for network elements is provided. According to one embodiment, a host network element executes a collection of security checks on at least a first network element. The execution is performed by receiving configuration data of the first network element pertaining to each security check of the collection of security checks in response to a request by the host network element and validating each security check by comparing the received configuration data pertaining to each security check with a pre-defined or configurable network security configuration recommendation to generate a compliance result. Further, the host network element generates a compliance report by aggregating the compliance results obtained by executing each security check of the collection of security checks.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Fortinet, Inc.
    Inventors: Robert A. May, Tarlok Birdi
  • Patent number: 11735531
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Publication number: 20230253332
    Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Inventors: Robert SANKMAN, Robert MAY
  • Patent number: 11721631
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Publication number: 20230208688
    Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.
    Type: Application
    Filed: November 21, 2022
    Publication date: June 29, 2023
    Inventors: Carlos Jesus Briseno-Vidrios, Michael Robert May, Patrick Johannus De Bakker
  • Patent number: 11658122
    Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Robert Sankman, Robert May
  • Publication number: 20230140389
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Applicant: Intel Corporation
    Inventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI