Patents by Inventor Robert Chau
Robert Chau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Patent number: 9666492Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.Type: GrantFiled: July 13, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau -
Publication number: 20160343844Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.Type: ApplicationFiled: August 4, 2016Publication date: November 24, 2016Inventors: Han Wui Then, Robert CHAU, Benjamin CHU-KUNG, Gilbert DEWEY, Jack KAVALIEROS, Matthew METZ, Niloy MUKHERJEE, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
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Publication number: 20160315153Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.Type: ApplicationFiled: June 29, 2016Publication date: October 27, 2016Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 9461160Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.Type: GrantFiled: December 19, 2011Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 9397188Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.Type: GrantFiled: November 9, 2015Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Publication number: 20160204276Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.Type: ApplicationFiled: September 25, 2013Publication date: July 14, 2016Inventors: Sansaptak DASGUPTA, Han Wui THEN, Sanaz GARDNER, Benjamin CHU-KUNG, Marko RADOSAVLJEVIC, Seung Hoon SUNG, Robert CHAU
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Publication number: 20160079359Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.Type: ApplicationFiled: November 19, 2015Publication date: March 17, 2016Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Publication number: 20160064512Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.Type: ApplicationFiled: November 9, 2015Publication date: March 3, 2016Inventors: Han Wui Then, Robert CHAU, Benjamin CHU-KUNG, Gilbert DEWEY, Jack KAVALIEROS, Matthew METZ, Niloy MUKHERJEE, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
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Patent number: 9245989Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.Type: GrantFiled: December 19, 2011Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 9240410Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.Type: GrantFiled: December 19, 2011Date of Patent: January 19, 2016Assignee: Intel CorporationInventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE
Publication number: 20150325481Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.Type: ApplicationFiled: July 13, 2015Publication date: November 12, 2015Inventors: Marko RADOSAVLJEVIC, Ravi PILLARISETTY, Gilbert DEWEY, Niloy MUKHERJEE, Jack KAVALIEROS, Willy RACHMADY, Van LE, Benjamin CHU-KUNG, Matthew METZ, Robert CHAU -
Publication number: 20150249131Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.Type: ApplicationFiled: May 8, 2015Publication date: September 3, 2015Inventors: BENJAMIN CHU-KUNG, VAN LE, ROBERT CHAU, SANSAPTAK DASGUPTA, GILBERT DEWEY, NITIKA GOEL, JACK KAVALIEROS, MATTHEW METZ, NILOY MUKHERJEE, RAVI PILLARISETTY, WILLY RACHMADY, MARKO RADOSAVLJEVIC, HAN WUI THEN, NANCY ZELICK
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CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Patent number: 9123567Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.Type: GrantFiled: December 19, 2011Date of Patent: September 1, 2015Assignee: Intel CorporationInventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau -
Patent number: 9048266Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: August 1, 2013Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
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Patent number: 9029835Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.Type: GrantFiled: December 20, 2012Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Benjamin Chu-King, Van Le, Robert Chau, Sansaptak Dasgupta, Gilbert Dewey, Nitika Goel, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy Zelick
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Patent number: 8872225Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.Type: GrantFiled: December 20, 2012Date of Patent: October 28, 2014Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Van Le, Robert Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy Zelick
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Publication number: 20140291663Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Inventors: Charles Kuo, Kaan Oguz, Brian Doyle, Elijah Ilya Karpov, Roksana Golizadeh Mojarad, David Kencke, Robert Chau
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Publication number: 20140175378Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van Le, Matthew Metz, Jack Kavalieros, RAVI PILLARISETTY, Sanaz Gardner, SANSAPTAK DASGUPTA, Willy Rachmady, BENJAMIN CHU-KUNG, MARKO RADOSAVLJEVIC, Gilbert Dewey, Marc French, JESSICA KACHIAN, SATYARTH SURI, Robert Chau
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Publication number: 20140175379Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: BENJAMIN CHU-KUNG, VAN LE, ROBERT CHAU, SANSAPTAK DASGUPTA, GILBERT DEWEY, NITIKA GOEL, JACK KAVALIEROS, MATTHEW METZ, NILOY MUKHERJEE, RAVI PILLARISETTY, WILLY RACHMADY, MARKO RADOSAVLJEVIC, HAN WUI THEN, NANCY ZELICK
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Publication number: 20140175512Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: BENJAMIN CHU-KUNG, VAN LE, ROBERT CHAU, SANSAPTAK DASGUPTA, GILBERT DEWEY, NITI GOEL, JACK KAVALIEROS, MATTHEW METZ, NILOY MUKHERJEE, RAVI PILLARISETTY, WILLY RACHMADY, MARKO RADOSAVLJEVIC, HAN WUI THEN, NANCY ZELICK