Patents by Inventor Robert Chau

Robert Chau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    Patent number: 7531404
    Abstract: A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 ? to 60 ?. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Sangwoo Pae, Jose Maiz, Justin Brask, Gilbert Dewey, Jack Kavalieros, Robert Chau, Suman Datta
  • Non-planar MOS structure with a strained channel region
    Patent number: 7531393
    Abstract: An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Suman Datta, Been-Yih Jin, Robert Chau
  • CONTROLLED INTERMIXING OF HFO2 AND ZRO2 DIELECTRICS ENABLING HIGHER DIELECTRIC CONSTANT AND REDUCED GATE LEAKAGE
    Publication number: 20090085082
    Abstract: Controlled deposition of HfO2 and ZrO2 dielectrics is generally described. In one example, a microelectronic apparatus includes a substrate and a dielectric film coupled with the substrate, the dielectric film including ZrO2 and HfO2 wherein the ratio of Zr to Hf in the dielectric film is about 5 to 10 atoms of Zr for every 1 atom of Hf to reduce ToxE or reduce Jox of the dielectric film.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Gilbert Dewey, Matthew Metz, Jack Kavalieros, Robert Chau
  • Methods for uniform doping of non-planar transistor structures
    Patent number: 7494862
    Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Robert Chau, Suman Datta, Jack Kavalieros
  • Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
    Patent number: 7473947
    Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Brian Doyle, Jack Kavalieros, Robert Chau
  • SEMICONDUCTOR ON INSULATOR APPARATUS
    Publication number: 20080303116
    Abstract: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.
    Type: Application
    Filed: August 20, 2008
    Publication date: December 11, 2008
    Inventors: Been-Yih Jin, Reza Arghavani, Robert Chau
  • High density memory
    Publication number: 20080237672
    Abstract: In one embodiment of the invention, a method of forming a semiconductor device includes forming a dynamic random access memory using spacer-defined lithography.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Brian S. Doyle, Dinesh Somasekhar, Robert Chau
  • Semiconductor on insulator apparatus and method
    Patent number: 7427538
    Abstract: A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Reza Arghavani, Robert Chau
  • Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
    Patent number: 7422971
    Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Brian Doyle, Jack Kavalieros, Robert Chau
  • Buffer architecture formed on a semiconductor wafer
    Publication number: 20080210927
    Abstract: In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 4, 2008
    Inventors: Mantu K. Hudait, Dmitri Loubychev, Suman Datta, Robert Chau, Joel M. Fastenau, Amy W. K. Liu
  • Semiconductor device having a metal gate electrode
    Patent number: 7420254
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal layer. Also described is a semiconductor device that comprises a metal gate electrode that is formed on a dielectric layer, which is formed on a substrate. The metal gate electrode includes a sufficient amount of an impurity to shift the workfunction of the metal gate electrode by at least about 0.1 eV.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: September 2, 2008
    Assignee: Intel Corporation
    Inventors: Robert Chau, Mark Doczy, Markus Kuhn
  • Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    Publication number: 20080169512
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 17, 2008
    Inventors: Brian S. Doyle, Suman Datta, Been-Yih Jin, Nancy M. Zelick, Robert Chau
  • Method of combining floating body cell and logic transistors
    Publication number: 20080157162
    Abstract: An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Brian S. Doyle, Suman Datta, Jack Kavalieros, Robert Chau
  • Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric
    Publication number: 20080151603
    Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.
    Type: Application
    Filed: February 28, 2008
    Publication date: June 26, 2008
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Justin Brask, Brian Doyle, Robert Chau
  • Nonplanar transistors with metal gate electrodes
    Publication number: 20080090397
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: November 21, 2007
    Publication date: April 17, 2008
    Inventors: Justin Brask, Brian Dovle, Jack Kavalleros, Mark Doczy, Uday Shah, Robert Chau
  • Forming high-K dielectric layers on smooth substrates
    Publication number: 20080087985
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Application
    Filed: November 29, 2007
    Publication date: April 17, 2008
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert Chau
  • Methods for uniform doping of non-planar transistor structures
    Publication number: 20080085580
    Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 10, 2008
    Inventors: Brian Doyle, Robert Chau, Suman Datta, Jack Kavalieros
  • Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    Patent number: 7348284
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Brian S Doyle, Suman Datta, Been-Yih Jin, Nancy M Zelick, Robert Chau
  • Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric
    Patent number: 7342277
    Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Justin Brask, Brian Doyle, Robert Chau
  • Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
    Publication number: 20080014730
    Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.
    Type: Application
    Filed: September 20, 2007
    Publication date: January 17, 2008
    Inventors: Reza Arghavani, Patricia Stokley, Robert Chau