Abstract: An orthopaedic surgical instrument includes a patella trial and drill guide that may be used to both perform a surgical trial of the patellofemoral joint and guide the surgeon in drilling a number of anchor holes in the patella of the patient.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: A radiography system includes a bed, having a surface for receiving and supporting a patient lying thereon, and an x-ray source positioned below the patient. A digital x-ray detector is positioned above the patient, facing the x-ray source, whereby the patient is positioned between the x-ray source and the detector. This configuration enables capturing an image of the patient exposed by the x-ray source.

Abstract: A temperature sensor circuit that includes two banks of bipolar transistors where the bipolar transistors of each bank are coupled in parallel in a current leg of the sensor circuit. The current legs are configured to produce voltages and currents that are dependent upon the temperature sensitivity of the bipolar transistors in the current legs. The sensor circuit includes a controller that, in some embodiments, periodically enables subsets of the bipolar transistors of each of bank during operation.

Abstract: A temperature sensor circuit that includes two banks of bipolar transistors where the bipolar transistors of each bank are coupled in parallel in a current leg of the sensor circuit. The current legs are configured to produce voltages and currents that are dependent upon the temperature sensitivity of the bipolar transistors in the current legs. The sensor circuit includes a controller that, in some embodiments, periodically enables subsets of the bipolar transistors of each of bank during operation.

Abstract: A circuit for high accuracy element matching is provided. The circuit includes an analog to digital converter (ADC) configured to generate an output code. A current source is configured to provide a signal to the ADC. The current source includes a first current branch including a first unit element group having a first unit element coupled by way of a first set of switches to a first node and a second node and a second unit element coupled by way of a second set of switches to the first node and the second node. A second current branch includes a second unit element group having a third unit element coupled by way of a third set of switches to the first node and the second node and a fourth unit element coupled by way of a fourth set of switches to the first node and the second node. A control circuit is configured to provide control signals to the sets of switches based on the output code. The control circuit is further configured to sort unit element currents and to dynamically switch unit elements.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

Abstract: An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array.

Abstract: An integrated circuit including a segmented successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitive structure with a first plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of a plurality of input voltage nodes and a second terminal connected to a common conductor, and second capacitive structure with a second plurality of capacitive structure subcomponents that each include a first terminal selectively connected to one of the plurality of input voltage nodes and a second terminal connected to the common conductor. The first and second plurality of capacitive structure subcomponents are arranged in an array in which none of the first plurality of capacitive structure subcomponents are directly adjacent to one another and none of the second plurality of capacitive structure subcomponents are directly adjacent to one another in a first row in the array.

Abstract: A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit.

Abstract: Vacuum insulating glass (VIG) units, edge seals for VIG units and methods for forming the edge seals are provided. The VIG units include an edge seal that includes a viscous material, which serves to restrict the rate at which gas permeates into a vacuum space defined between the glass sheets of the VIG unit. The edge seals are configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets.

Abstract: Vacuum insulating glass (VIG) units and edge seals for VIG units are provided. The VIG units include an edge seal that includes a viscous material, and is configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets. The edge seals comprise a cavity that contains at least a portion of the viscous material, wherein at least a portion of a boundary defining the cavity is reversibly expandable and collapsible such that the viscous material and the cavity are configured to maintain volume compatibility when one or both of the viscous material and the cavity undergo a temperature-induced volume change.

Abstract: The apparatus is a mechanism for acquiring, holding, and enabling the movement of a cassette-shaped article, such as a reagent or sample cassette, which may be part of an automated diagnostic analyzer, such that the apparatus can tolerate a significant degree of cassette misplacement and/or misalignment during the acquisition maneuver. The mechanism furthermore enables simultaneous two-dimensional movement of the acquiring gripper jaws such that the inter-jaw distance decreases at the same time as movement in an upward vertical direction is provided while the jaw movement is adequately smooth so as not to disturb the physical state of the sample.

Abstract: The invention relates generally to an apparatus for acquiring, holding, and enabling the movement of a cassette-shaped article, such as a reagent or sample cassette, which may be part of an automated diagnostic analyzer, such that the apparatus can tolerate a significant degree of cassette misplacement and/or misalignment during the acquisition maneuver. The invention provides simultaneous two-dimensional movement of the acquiring gripper jaws such that the inter-jaw distance decreases at the same time as movement in an upward vertical direction is provided while the jaw movement is adequately smooth so as not to disturb the physical state of the sample.

Abstract: The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.

Abstract: The apparatus is a mechanism for acquiring, holding, and enabling the movement of a cassette-shaped article, such as a reagent or sample cassette, which may be part of an automated diagnostic analyzer, such that the apparatus can tolerate a significant degree of cassette misplacement and/or misalignment during the acquisition maneuver. The mechanism furthermore enables simultaneous two-dimensional movement of the acquiring gripper jaws such that the inter-jaw distance decreases at the same time as movement in an upward vertical direction is provided while the jaw movement is adequately smooth so as not to disturb the physical state of the sample.

Abstract: Vacuum systems comprising vacuum insulating glass (VIG) units are provided. The vacuum spaces within the VIG units are connected to one another and to one or more vacuum pumps that are configured to operate during the service lives of the VIG units.

Abstract: Vacuum systems comprising vacuum insulating glass (VIG) units are provided. The vacuum spaces within the VIG units are connected to one another and to one or more vacuum pumps that are configured to operate during the service lives of the VIG units.