Patents by Inventor Robert S. Jones

Robert S. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860596
    Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) includes an amplifier, a first variable capacitance circuit coupled to a first input to the amplifier, a second variable capacitance circuit coupled to a second input to the amplifier, a third variable capacitance circuit coupled to a first output of the amplifier, and a fourth variable capacitance circuit coupled to a second output of the amplifier. An output of the third and fourth capacitance circuits are coupled to one another and to inputs to the first and second variable capacitance circuits. Capacitance values of the first, second, third and fourth variable capacitance circuits are higher when inputs to the ADC correspond to a selected number of more significant bits than when inputs to the ADC correspond to a remaining number of less significant bits.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert S. Jones, Peijun Wang
  • Patent number: 8791847
    Abstract: A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peijun Wang, Robert S. Jones
  • Publication number: 20140203955
    Abstract: A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Inventors: PEIJUN WANG, Robert S. Jones
  • Publication number: 20140116516
    Abstract: Vacuum systems comprising vacuum insulating glass (VIG) units are provided. The vacuum spaces within the VIG units are connected to one another and to one or more vacuum pumps that are configured to operate during the service lives of the VIG units.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 1, 2014
    Inventor: Robert S. Jones
  • Patent number: 8525721
    Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) receives a high voltage (VRH) and a low voltage (VRL) for use in converting an input signal to a digital signal. A doubling circuit receives the input signal and doubles the input signal to provide a doubled input signal using an amplifier and a first capacitor. The first capacitor has a capacitance of a first magnitude. A VR circuit continues processing the doubled input signal to provide a 2VR signal. A Vref circuit (VR+C5 and C6) provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal. The first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage. The second capacitor has a capacitance equal to half that of the first capacitor.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Robert S. Jones, III
  • Publication number: 20130101759
    Abstract: Vacuum insulating glass (VIG) units and edge seals for VIG units are provided. The VIG units include an edge seal that includes a viscous material, and is configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets. The edge seals comprise a cavity that contains at least a portion of the viscous material, wherein at least a portion of a boundary defining the cavity is reversibly expandable and collapsible such that the viscous material and the cavity are configured to maintain volume compatibility when one or both of the viscous material and the cavity undergo a temperature-induced volume change.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 25, 2013
    Inventor: Robert S. Jones
  • Publication number: 20130069811
    Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) receives a high voltage (VRH) and a low voltage (VRL) for use in converting an input signal to a digital signal. A doubling circuit receives the input signal and doubles the input signal to provide a doubled input signal using an amplifier and a first capacitor. The first capacitor has a capacitance of a first magnitude. A VR circuit continues processing the doubled input signal to provide a 2VR signal. A Vref circuit (VR+C5 and C6) provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal. The first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage. The second capacitor has a capacitance equal to half that of the first capacitor.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Inventor: ROBERT S. JONES, III
  • Publication number: 20120315409
    Abstract: Vacuum insulating glass (VIG) units, edge seals for VIG units and methods for forming the edge seals are provided. The VIG units include an edge seal that includes a viscous material, which serves to restrict the rate at which gas permeates into a vacuum space defined between the glass sheets of the VIG unit. The edge seals are configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets.
    Type: Application
    Filed: August 1, 2012
    Publication date: December 13, 2012
    Inventor: Robert S. Jones
  • Patent number: 8248288
    Abstract: An analog to digital converter has an input circuit, a computation circuit, an initialization circuit, and an output circuit. The input circuit is for receiving an analog signal and has a pair of outputs. A computation circuit has a pair of inputs coupled to the pair of outputs. The computation circuit has an amplifier having a pair of complementary outputs (Outp, Outn). The initialization circuit is coupled to the complementary outputs and is for biasing the complementary outputs at a time prior to the computation circuit beginning a computation on the analog signal. The output circuit is coupled to the pair of complementary outputs and provides a digital signal.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: August 21, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Juxiang Ren, Robert S. Jones
  • Publication number: 20120202075
    Abstract: Vacuum insulating glass (VIG) units, edge seals for VIG units and methods for forming the edge seals are provided. The VIG units include an edge seal that includes a viscous material, which serves to restrict the rate at which gas permeates into a vacuum space defined between the glass sheets of the VIG unit. The edge seals are configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 9, 2012
    Inventor: Robert S. Jones
  • Patent number: 8182887
    Abstract: Vacuum insulating glass (VIG) units, edge seals for VIG units and methods for forming the edge seals are provided. The VIG units include an edge seal that includes a viscous material, which serves to restrict the rate at which gas permeates into a vacuum space defined between the glass sheets of the VIG unit. The edge seals are configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: May 22, 2012
    Inventor: Robert S. Jones
  • Publication number: 20110236609
    Abstract: Vacuum insulating glass (VIG) units, edge seals for VIG units and methods for forming the edge seals are provided. The VIG units include an edge seal that includes a viscous material, which serves to restrict the rate at which gas permeates into a vacuum space defined between the glass sheets of the VIG unit. The edge seals are configured to allow the glass sheets to move laterally relative to one another when the glass sheets experience differential thermal strain and further configured such that viscous shear occurs within at least a portion of the viscous material when there is relative lateral movement between the glass sheets.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 29, 2011
    Inventor: Robert S. Jones
  • Publication number: 20100321226
    Abstract: An analog to digital converter has an input circuit, a computation circuit, an initialization circuit, and an output circuit. The input circuit is for receiving an analog signal and has a pair of outputs. A computation circuit has a pair of inputs coupled to the pair of outputs. The computation circuit has an amplifier having a pair of complementary outputs (Outp, Outn). The initialization circuit is coupled to the complementary outputs and is for biasing the complementary outputs at a time prior to the computation circuit beginning a computation on the analog signal. The output circuit is coupled to the pair of complementary outputs and provides a digital signal.
    Type: Application
    Filed: February 27, 2008
    Publication date: December 23, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Juxiang Ren, Robert S. Jones
  • Patent number: 7589658
    Abstract: An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: September 15, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Juxiang Ren, Mike R. Garrard, Robert S. Jones, III, Douglas A. Garrity
  • Publication number: 20090195428
    Abstract: An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 6, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Juxiang Ren, Mike R. Garrard, Robert S. Jones, III, Douglas A. Garrity
  • Patent number: 7558677
    Abstract: A method of coordinating surveys of different origins and which may be projected into different coordinate systems. The method provides a translation and rotation of the surveys to be coordinated without disturbing the internal geometry of each survey. A geographic information system including a procedure for coordinating surveys of different origins and/or which surveys which projected in different coordinate systems.
    Type: Grant
    Filed: December 9, 2007
    Date of Patent: July 7, 2009
    Assignee: R.A. Smith National, Inc.
    Inventor: Robert S. Jones
  • Patent number: 7558678
    Abstract: A method of coordinating surveys of different origins and which may be projected into different coordinate systems. The method provides a translation and rotation of the surveys to be coordinated without disturbing the internal geometry of each survey. A geographic information system including a procedure for coordinating surveys of different origins and/or which surveys which projected in different coordinate systems.
    Type: Grant
    Filed: December 9, 2007
    Date of Patent: July 7, 2009
    Assignee: R.A. Smith National, Inc.
    Inventor: Robert S. Jones
  • Patent number: 7558676
    Abstract: A method of coordinating surveys of different origins and which may be projected into different coordinate systems. The method provides a translation and rotation of the surveys to be coordinated without disturbing the internal geometry of each survey. A geographic information system including a procedure for coordinating surveys of different origins and/or which surveys which projected in different coordinate systems.
    Type: Grant
    Filed: December 9, 2007
    Date of Patent: July 7, 2009
    Assignee: R.A. Smith National, Inc.
    Inventor: Robert S. Jones
  • Publication number: 20080154508
    Abstract: A method of coordinating surveys of different origins and which may be projected into different coordinate systems. The method provides a translation and rotation of the surveys to be coordinated without disturbing the internal geometry of each survey. A geographic information system including a procedure for coordinating surveys of different origins and/or which surveys which projected in different coordinate systems.
    Type: Application
    Filed: December 9, 2007
    Publication date: June 26, 2008
    Inventor: Robert S. Jones
  • Patent number: D653727
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 7, 2012
    Assignee: Pentair Pump Group, Inc.
    Inventors: Michael D. Catanzaro, Raleigh Lee Cox, Christopher Edward Cox, Jason J. Davis, Robert S. Jones