Abstract: A semiconductor device includes: a channel having layers of silicon separated from each other; a metal gate in contact with the layers of silicon; source/drain regions adjacent to the metal gate; a frontside power rail extending through the layers of silicon; a dielectric separating the frontside power rail from the metal gate; a via-connect buried power rail extending through the dielectric and coupling the frontside power rail to the source/drain regions; and a backside power rail coupled to the frontside power rail. The layers of silicon are wrapped on three sides by the metal gate.

Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

Abstract: A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Abstract: Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.

Abstract: A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Abstract: A contact structure having reduced middle-of-the-line (MOL) resistance is provided that includes a source/drain contact which includes a liner and a via contact that is liner-less. The via contact includes a first via portion having a first critical dimension and a second via portion having a second critical dimension that is greater than the first critical dimension. The second critical dimension provides a maximized via contact bottom critical dimension over the source/drain contact, while the first critical dimension provides sufficient area between the first via portion of the via contact and a neighboring electrically conductive structure thus avoiding any shorts between those two elements.

Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.

Abstract: A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

Abstract: Embodiments of present invention provide a method of improving yield of making MRAM arrays. More specifically, the method includes receiving an MRAM array; identifying a weak MRAM cell from the MRAM array wherein the weak MRAM cell includes an access transistor; and modifying the access transistor. In one embodiment, modifying the access transistor includes performing a hot carrier injection into a gate dielectric layer of the access transistor.

Abstract: Embodiments of the invention include a method for fabricating a magnetoresistive random-access memory (MRAM) structure and the resulting structure. A first type of metal is formed on an interlayer dielectric layer with a plurality of embedded contacts, where the first type of metal exhibits spin Hall effect (SHE) properties. At least one spin-orbit torque (SOT) MRAM cell is formed on the first type of metal. One or more recesses surrounding the at least one SOT-MRAM cell are created by recessing exposed portions of the first type of metal. A second type of metal is formed in the one or more recesses, where the second type of metal has lower resistivity than the first type of metal.

Abstract: A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring, a second level of interconnect wiring disposed above the first level of interconnect wiring, a third level of interconnect wiring disposed above the second level of interconnect wiring, and a skip via extending from the third level of interconnect wiring to the first level of interconnect wiring such that a sidewall of the skip via maintains electrical contact with the second level of interconnect wiring. A contact area between the sidewall of the skip via and the second level of interconnect wiring is greater than a contact area between a bottom portion of the skip via and a top portion of the first level of interconnect wiring.

Abstract: A semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. The capacitor structure includes first and second electrode layers separated by a dielectric layer. A top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. A spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.

Abstract: A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

Abstract: A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.