Abstract: An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.

Abstract: A semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. A bottom dielectric isolation region is located inward of the gate. First and second bottom silicon regions are respectively located inward of the first and second source-drain regions. A back side contact projects through the second bottom silicon region into the second source-drain region.

Abstract: A semiconductor device includes power rails formed in a backside of a wafer. A gate of a first transistor on the wafer is connected to a power rail through a via-to-backside power rail (VBPR) gate contact. A source/drain (S/D) region of a second transistor on the wafer is connected to a power rail through a VBPR S/D contact. The VBPR gate contact partially vertically overlaps a gate cut region between the first transistor and the second transistor.

Abstract: A semiconductor device that includes a stack of sheet semiconductor layers, and source and drain regions positioned on opposing sides of a channel region in the stack of sheet semiconductor layers. A first contact is present to an upper sheet portion of the source and drain regions for the stack of sheet semiconductor layers. An extended epitaxial semiconductor region is present in contact with the lower sheet portion of the source/drain regions for the stack of sheet semiconductor layers. A second contact is present in direct contact with an upper surface of the extended epitaxial semiconductor region. A notch may be present in the upper surface of the extended semiconductor region to increase contact surface to the second contact.

Abstract: Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

Abstract: Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer that includes a first transistor device. A first back-end-of-line (BEOL) layer is on a front side of the FEOL layer and includes a first electrical connection to the first transistor device. A second BEOL layer is on a back side of the FEOL layer and includes a first BEOL device with a second electrical connection to the first transistor device.

Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extends vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region extends below a bottom surface of the gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.

Abstract: A semiconductor device a first device located on a frontside of a semiconductor substrate. The semiconductor device further includes an inductor located on a backside of the semiconductor substrate and integrated with a first backside metal (BSM) stack. The semiconductor device further includes a first electrical contact located between the frontside and the backside of the semiconductor substrate. A first end of the first electrical contact is connected to the first BSM stack and a second end of the first electrical contact is connected to a first source/drain region of the first device.

Abstract: A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Abstract: A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer.

Abstract: Self-aligned direct backside contacts by an epitaxy everywhere under source/drain region approach are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a backside interlayer dielectric; an epitaxial contact placeholder in the backside interlayer dielectric that directly contacts a first source/drain region of the field-effect transistor(s); and a self-aligned direct backside contact in the backside interlayer dielectric that directly contacts a second source/drain region of the field-effect transistor(s). The epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first source/drain region, and the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second source/drain region, where d2>d1. The field-effect transistor(s) can include a stack of active layers surrounded by a gate, and the first/second source/drain regions on opposite sides thereof.

Abstract: A semiconductor device includes a wafer having at least two source/drain (S/D) epi regions. A power rail is arranged on a backside of the wafer. A backside contact (BSCA) has a first portion including a backside local interconnect configured to connect the S/D epi regions together. A plurality of frontside signal wires are connected to the backside local interconnect through a first front side contact.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: An approach to form a semiconductor structure with a plurality of buried power rails in a semiconductor substrate where at least one buried power rail extends below the backside of the semiconductor substrate. The semiconductor structure provides at least one portion of the first metal layer of the backside power delivery network that surrounds a bottom portion of the buried power rail below the backside of the semiconductor substrate. The bottom portion of the buried power rail is in direct contact with the portion of the first metal layer of the backside power delivery network where the buried power rail and the first metal layer are composed of the same conductive material. The semiconductor structure includes a portion of an interlayer dielectric material isolating the first metal layer of the backside power distribution network from the backside of the semiconductor substrate.