Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: A computing cable comprising a trace having a first impedance and an attenuator that includes a fixed resistor having a second resistance, a variable resistor having a first resistance, and a conductor having a second impedance. The combination of the first resistance, the second resistance, and the second impedance is based on the first impedance, wherein the first resistance is varied dynamically at runtime based on a control input.

Abstract: A printed circuit board (PCB) includes an array of signal pads on a first surface of the PCB, a power contact pad on the first surface, and a ground contact pad on a second surface of the PCB. Each signal pad of the array of signal pads is associated with a signal contact of a central processing unit (CPU). The power contact pad provides power for the CPU apart from the array of signal pads. The ground contact pad provides a ground for the CPU apart from the array of signal pads.

Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: Chlorotoxin derivatives containing amino acid sequence X0X1CMPCXS1XS2XS3DHXS4XS5ARRCX2X3CCGGYGX4CFGYQC LCX5X6X7X8 wherein (i) the N-terminal X0X1 cluster is AM, 0M, or 00; (ii) the solubility XS1XS2XS3XS4XS5 cluster is FTTQT, FTTES, SSSQT, SSSES, FSSQT, FSSES, or FSSQS; (iii) the internal X2X3X4 cluster is DKR, RDK, KDR, IKY, HKW, DRK, LKQ, KKK; and (iv) the C-terminal X5X6X7X8 cluster is N000, R000, NR00, NRG0, NRGY, NRRR, or RRRR; 0 denotes a position where no amino acid is present; the chlorotoxin derivative has a relative human MMP-2 binding that is at least 1.62 times higher than the wild-type chlorotoxin of SEQ ID NO: 1.

Abstract: A printed circuit board includes a first and second microstrip circuit traces formed on an outer surface of the printed circuit board, and a patterned dielectric material applied over a first length of the first microstrip circuit trace. The first microstrip circuit trace has a first length and carries a first signal. The second microstrip circuit trace is adjacent to the first microstrip circuit trace, has a second length longer than the first length, and carries a second signal. The patterned dielectric material is provided over a portion of the first length to delay the first signal relative to the second signal.

Abstract: A printed circuit board includes first and second insulating layers, first and second strip line circuit traces formed on a surface of the first insulating layer, and a patterned dielectric material. The first strip line circuit trace has a first length and carries a first signal. The second strip line circuit trace is adjacent to the first strip line circuit trace, has a second length longer than the first length, and carries a second signal. The patterned dielectric material is provided over a portion of the first length to delay the first signal relative to the second signal. The second insulating layer is affixed to the surface and covers the first and second strip line circuit traces and the patterned dielectric material.

Abstract: A printed circuit board includes metal layers, a metalized circuit via interconnecting a first one of the metal layers and a second one of the metal layers, and a back-drill hole drilled to remove metalization of the circuit via from a third metal layer adjacent to the second metal layer to a fourth metal layer at a first surface of the printed circuit board. The back-drill hole has a profile that includes a first undercut at a bottom of the first back-drill hole.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.

Abstract: A data communications cable may communicatively coupled two components associated with an information handling system. For example, the data communications cable may include: a differential pair of conductors; a first dielectric material, associated with a first relative permittivity, surrounding the differential pair of conductors; and a second dielectric material, associated with a second relative permittivity, surrounding the first dielectric material. For instance, the first relative permittivity may be greater than the second relative permittivity, and a distance between the differential pair of conductors may vary plus or minus an amount with a length of the data communications cable.

Abstract: Compensating for signal loss, including determining a first expected loss at a first frequency and a second expected loss at a second frequency at a receiver associated with a first lane of a PCB; calculating an expected rate of change of signal loss between the first and the second frequencies based on the first and the second expected losses; calculating a first measured loss of a first signal transmitted at the first frequency and a second measured loss of a second signal transmitted at the second frequency from a transmitter to the receiver along the first lane of the PCB; calculating a measured rate of change of signal loss between the first and second frequencies based on the first and the second measured losses; comparing the measured rate of change with the expected rate of change; compensating a gain of a signal transmitted from the transmitter to the receiver.

Abstract: A memory module socket, including a first member extending between a first end and a second end of the socket, the second end of the socket opposite to the first end of the socket, the first member positioned along a first side of the socket, the first member including: a plurality of first contact pins, each of the first contact pins including a first contact point and a second contact point; a plurality of first resistive coatings connecting two or more of the first contact pins to define first groupings of contact pins; a plurality of first ribs separating each of the first groupings of first contact pins; wherein when the first contact pins are in a first position, the second contact points of the first contact pins are in contact with respective first resistive coatings to complete a termination to ground.

Abstract: An apparatus includes a first conductor trace arranged to electrically couple a first complementary signal to provide differential signaling. The first conductor trace includes a first plurality of split traces to conduct the first complementary signal, and a first plurality of tie bars to connect the first split traces.

Abstract: A printed circuit board (PCB) includes a metal layer and a via. The via is coupled to a portion of the metal layer. The portion of the metal layer forms a flange of a beam structure in the PCB. The via forms a web of the beam structure in the PCB.

Abstract: A printed circuit board of an information handling system includes a pair of signal vias including a pair of keepout objects. Each one of the keepout objects surrounds one of the signal vias. The printed circuit board includes a pair of signal traces that includes a positive signal trace and a negative signal trace, wherein the pair of signal traces are between the keepout objects, and wherein a width of each of the signal traces is increased.

Abstract: An information handling system includes a printed circuit board, which in turn includes a differential pair, a ground trace, and a ground via. The differential pair includes first and second traces. The ground trace is routed between the first and second traces of the differential pair. The ground via is located along the ground trace. The ground trace and the ground via combine to create a common mode signal filter, which in turn resets a skew of the differential pair.

Abstract: A cable comprising a conductor in a center of the cable, a dielectric layer surrounding the conductor and a resistive coating may be provided. The resistive coating may be applied to an exposed portion of the conductor and disposed with the dielectric layer. The resistance of the resistive coating when combined with an impedance of the cable prior to application of the resistive coating reaches a target impedance.

Abstract: A computing cable that connects computing elements, including: a trace including a first trace segment and a second trace segment, the trace having a first impedance; and an attenuator connecting the first trace segment to the second trace segment, the attenuator including: a resistor having a resistance, and a conductor having a second impedance, wherein the combination of the resistance and the second impedance is based on the first impedance.

Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: An information handling system includes a PCB, a CPU, a power distribution hat, and a heat sink. The PCB includes a first power contact on a first surface of the PCB and a first ground contact on a second surface of the PCB. The CPU includes a substrate and is affixed and electrically coupled to the first surface of the PCB by a first surface of the substrate. A second surface of the substrate includes a second power contact and a second ground contact. The power distribution hat couples the first power contact with the second power contact. The heat sink couples the first ground contact with the second ground contact.