Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A likely value is calculated by a maximum-likelihood method for all coefficients of a relative error correction circuit network model derived by assuming that, for all pairs of two ports selected from among signal line ports related to application or detection of a high frequency signal and non signal line ports other than the signal line ports, there exists a leak signal directly transferred between the ports. A coefficient of a first relative error correction circuit network submodel derived by assuming that, for all pairs of two ports selected only from among signal line ports, there exists a leak signal directly transferred between the ports, and a coefficient for a non signal line port of a second relative error correction circuit network submodel derived by assuming that there exists a signal reflected at a non signal line port are used as initial values.

Abstract: A first S parameter of a first circuit network including an input port and a connection port is prepared, a second S parameter of a second circuit network is measured, and an overall S parameter of an overall circuit network is calculated. The S parameter of the overall circuit network is calculated as the overall S parameter corresponding to the input port among virtual S parameters of a virtual overall circuit network in which the connection port of the virtual first circuit network is connected with the second circuit network, by using, as an unknown value, a parameter corresponding to the dummy port among virtual T parameters of a virtual first circuit network obtained through conversion of the first circuit network into a symmetric circuit network by adding a dummy port to the input port side of the first circuit network.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

Abstract: The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer.

Abstract: A first S parameter of a first circuit network including an input port and a connection port is prepared, a second S parameter of a second circuit network is measured, and an overall S parameter of an overall circuit network is calculated. The S parameter of the overall circuit network is calculated as the overall S parameter corresponding to the input port among virtual S parameters of a virtual overall circuit network in which the connection port of the virtual first circuit network is connected with the second circuit network, by using, as an unknown value, a parameter corresponding to the dummy port among virtual T parameters of a virtual first circuit network obtained through conversion of the first circuit network into a symmetric circuit network by adding a dummy port to the input port side of the first circuit network.

Abstract: A likely value is calculated by a maximum-likelihood method for all coefficients of a relative error correction circuit network model derived by assuming that, for all pairs of two ports selected from among signal line ports related to application or detection of a high frequency signal and non signal line ports other than the signal line ports, there exists a leak signal directly transferred between the ports. A coefficient of a first relative error correction circuit network submodel derived by assuming that, for all pairs of two ports selected only from among signal line ports, there exists a leak signal directly transferred between the ports, and a coefficient for a non signal line port of a second relative error correction circuit network submodel derived by assuming that there exists a signal reflected at a non signal line port are used as initial values.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

Abstract: The present invention provides an electronic device that is able to achieve an improvement in yield or an electronic device that is able to prevent a sealing resin from exfoliating from a sub-electrode. The electronic device is provided with an electronic element and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The bonding pad includes a Pd layer that directly contacts the wire.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.