Patents by Inventor Satoshi Kageyama

Satoshi Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9240439
    Abstract: A semiconductor device includes a first etching stopper film and a second etching stopper film that are formed to be spaced apart from one another on a first inter-layer insulating film; a metal thin film resistor formed to extend over the first and second etching stopper films; a second inter-layer insulating film formed on the first inter-layer insulating film to cover the first and second etching stopper films and the metal thin film resistor; a first contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the first etching stopper film by penetrating through the metal thin film resistor; and a second contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the second etching stopper film by penetrating through the metal thin film resistor.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 19, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Ryoutaro Yagi, Satoshi Kageyama
  • Publication number: 20160013143
    Abstract: The present invention provides an electronic device that is able to achieve an improvement in yield or an electronic device that is able to prevent a sealing resin from exfoliating from a sub-electrode. The electronic device is provided with an electronic element and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The bonding pad includes a Pd layer that directly contacts the wire.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 14, 2016
    Inventors: Kenji FUJII, Satoshi KAGEYAMA
  • Patent number: 9184132
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 10, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Publication number: 20150287678
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Patent number: 9082769
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 14, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Patent number: 9064927
    Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: June 23, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20150162396
    Abstract: A semiconductor device includes a first etching stopper film and a second etching stopper film that are formed to be spaced apart from one another on a first inter-layer insulating film; a metal thin film resistor formed to extend over the first and second etching stopper films; a second inter-layer insulating film formed on the first inter-layer insulating film to cover the first and second etching stopper films and the metal thin film resistor; a first contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the first etching stopper film by penetrating through the metal thin film resistor; and a second contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the second etching stopper film by penetrating through the metal thin film resistor.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 11, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Ryoutaro YAGI, Satoshi KAGEYAMA
  • Publication number: 20150137314
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 21, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
  • Publication number: 20150061145
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi KAGEYAMA, Masaru NAITOU
  • Patent number: 8912657
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 16, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Publication number: 20140299990
    Abstract: The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 9, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Isamu NISHIMURA
  • Publication number: 20140091431
    Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.
    Type: Application
    Filed: November 26, 2013
    Publication date: April 3, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Patent number: 8647984
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 8618634
    Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: December 31, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20130300001
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 14, 2013
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Patent number: 8508033
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: August 13, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Patent number: 8395236
    Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: March 12, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20120199942
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Publication number: 20120199946
    Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Patent number: 8227922
    Abstract: A semiconductor device includes a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring and having a laminated structure including an SiCO layer and an SiCN layer; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film; an upper wiring layer laminated on the intermediate film and having an upper groove formed in a top surface thereof; an upper layer wiring embedded in the upper groove and made of a metal material having Cu as a main component; and a via electrically connecting the lower layer wiring and the upper layer wiring and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: July 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama