Patents by Inventor Satoshi Kageyama

Satoshi Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7750480
    Abstract: The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material mainly composed of Cu, penetrating through the intermediate dielectric film to be connected to the first wire and the second wire; and a dummy via, made of a material mainly composed of Cu, smaller in via diameter than the via and connected to the first wire while not contributing to electrical connection between the first wire and the second wire.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: July 6, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20100035428
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 11, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi Kageyama, Yoshihisa Takada
  • Publication number: 20100032837
    Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion
    Type: Application
    Filed: October 11, 2007
    Publication date: February 11, 2010
    Applicant: ROHM CO., LTD
    Inventors: Ryosuke Nakagawa, Takahisa Yamaha, Yuichi Nakao, Katsumi Sameshima, Satoshi Kageyama
  • Publication number: 20090189282
    Abstract: A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed on the high dielectric layer and made of an insulating material differing from the low dielectric material and the high dielectric material; a groove formed by digging in from an upper surface of the protective layer to the low dielectric layer; a barrier film coated onto a bottom surface and side surfaces of the groove and made of a material having a barrier property with respect to diffusion of Cu; and a wiring formed on the barrier film, made of a metal material having Cu as a main component, and completely filling the groove.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 30, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Yoshihisa Takada, Satoshi Kageyama
  • Publication number: 20090115062
    Abstract: A semiconductor device according to the present invention includes: a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film; an upper wiring layer laminated on the intermediate film; an upper layer wiring made of a metal material having Cu as a main component and embedded in an upper groove formed by digging in from a top surface of the upper wiring layer; and a via for electrically connecting the lower layer wiring and the upper layer wiring made of the same material as the material of the upper layer wiring and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 7, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20090108404
    Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Publication number: 20090102057
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 23, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Yuichi Nakao
  • Publication number: 20090079086
    Abstract: A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface.
    Type: Application
    Filed: August 6, 2008
    Publication date: March 26, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Publication number: 20090072405
    Abstract: The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material mainly composed of Cu, penetrating through the intermediate dielectric film to be connected to the first wire and the second wire; and a dummy via, made of a material mainly composed of Cu, smaller in via diameter than the via and connected to the first wire while not contributing to electrical connection between the first wire and the second wire.
    Type: Application
    Filed: September 2, 2008
    Publication date: March 19, 2009
    Applicant: ROHM CO.,LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20090032953
    Abstract: A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween.
    Type: Application
    Filed: May 30, 2008
    Publication date: February 5, 2009
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20080290517
    Abstract: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface of the wiring trench, Cu wiring mainly composed of Cu embedded in the wiring trench, and a second barrier film made of a compound containing Si, O and a predetermined metallic element covering the surface of the Cu wiring opposed to the wiring trench.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 27, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20080265370
    Abstract: In the semiconductor device according to the present invention, a lower electrode and an upper electrode are relatively positionally deviated from each other through a capacitance film in a direction perpendicular to the laminating direction thereof. Thus, the upper electrode and the lower electrode each have portions opposed to each other through the capacitance film in the laminating direction and portions not opposed to each other. An upper electrode plug is connected to the portion of the upper electrode not opposed to the lower electrode through an upper electrode contact hole passing through an insulating film formed on the upper electrode. Further, a lower electrode plug is connected to the portion of the lower electrode not opposed to the upper electrode through a lower electrode contact hole passing through the insulating film.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 30, 2008
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20080251929
    Abstract: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.
    Type: Application
    Filed: October 21, 2005
    Publication date: October 16, 2008
    Inventor: Satoshi Kageyama
  • Publication number: 20080237870
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: November 7, 2007
    Publication date: October 2, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Publication number: 20070173725
    Abstract: A method of processing skin surface observation measuring data able to address various sicknesses and reduce an error in sickness detection, and a measuring apparatus requiring no filter with a simple structure. The measuring apparatus comprises a means of applying a white light to a biological surface as a sample, a means of detecting the spectra of the white light reflected off a plurality of positions on the biological surface, a means of plotting the absorbances of the above spectra to a light spectrum multi-dimensional space, a means of subjecting data in the spectrum multi-dimension space obtained from the plurality of positions to multivariate analysis to determine the eigenvectors of at least first, second and third principal components, and a means of projecting data at respective positions in respective eigenvector directions to display their magnitudes on a two-dimension display screen on a gray scale or in colors corresponding to the magnitudes; and a measuring method by the apparatus.
    Type: Application
    Filed: February 22, 2005
    Publication date: July 26, 2007
    Applicant: Waseda University
    Inventors: Takayuki Souta, Katsuo Aizawa, Atsushi Nakamura, Satoshi Kageyama, Shinya Ohtsubo, Fumihiko Ichikawa
  • Patent number: 6169040
    Abstract: A USG layer 26 is formed to cover an aluminum wiring 24 deposited a field oxide film 22. An organic SOG layer 28 whose thick layer can be easily formed is formed in a groove on the surface of the USG layer 26. Thus, the unevenness of the surface of the USG layer 26 can be relaxed in a degree. Further, an USG layer 30 is formed thereon is formed through the vapor phase growth technique using the high density plasma which can realize excellent embedding. Accordingly, the inter-metal dielectric film 32 having a flat upper surface can be formed. Further, the SOG step is carried out only once in the step of forming the organic SOG layer 28, thereby reducing the production cost. Further, since the organic SOG layer 28 can be encircled by the USG layers 26 and 39 having good film quality, even if the material of the organic SOG layer 28 is not so good, the inter-metal dielectric film 32 with an excellent dielectric property can be formed.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: January 2, 2001
    Assignee: Rohm Co., Ltd.
    Inventors: Michihiko Mifuji, Satoshi Kageyama
  • Patent number: 5850460
    Abstract: Passive radiators of the same effective vibration area and the same effective vibration mass disposed in mutual opposition, and driver units of the same effective vibration area and the same effective vibration mass disposed in mutual opposition, are mounted to a bandpass type enclosure. The vibration-reaction forces of the opposing passive radiators and opposing driver units on the enclosure are thereby mutually cancelled, and enclosure vibrations are thus greatly reduced. Powerful bass output can be achieved because the diameter of the passive radiators can be increased at will and the use of two passive radiators achieves an extremely large vibration area.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: December 15, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoji Tanaka, Kazuaki Tamura, Satoshi Kageyama
  • Patent number: 5588065
    Abstract: A bass reproduction speaker apparatus of the present invention includes: a cabinet with an opening, having a division member inside thereof; a speaker unit disposed at the division member; a passive radiator disposed in the opening; an amplifier for driving the speaker unit; a detector for detecting a vibration of a moving system of the speaker unit; and a feedback circuit for feeding back an output signal from the detector to the amplifier.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 24, 1996
    Assignee: Masushita Electric Industrial Co.
    Inventors: Shoji Tanaka, Katsuhiko Iimura, Satoshi Kageyama
  • Patent number: 5140460
    Abstract: A motion-picture screen for projecting an optical image, which comprises a weaved knit having an adequate air permeability. One surface of the weaved knit is coated with a colored material so as to keep a high acoustic permeability concurrently with shutting the light from a wall or the like existing at the rear side of the screen. The other surface of the weaved knit is used as a surface onto which the optical image is projected by a projector, thereby providing an excellent contrast and a high image quality on the screen.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: August 18, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Suemei Fukuhara, Satoshi Kageyama
  • Patent number: 5073945
    Abstract: An improved dipole type characteristic loudspeaker system has a pair of loudspeakers (1 and 2) which are mounted on the front baffle board (4) and the back baffle board (5) of a console (3) and are connected to be driven in each-other opposite phase relation and have substantially the same acoustic characteristics in the medium and high frequency range but different acoustic characteristic in low frequency range; such loudspeaker system produces good surround-sound effect when used as back loudspeakers only with small number.
    Type: Grant
    Filed: July 23, 1990
    Date of Patent: December 17, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Kageyama, Suemei Fukuhara