Patents by Inventor Satoshi Kageyama

Satoshi Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8198732
    Abstract: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface of the wiring trench, Cu wiring mainly composed of Cu embedded in the wiring trench, and a second barrier film made of a compound containing Si, O and a predetermined metallic element covering the surface of the Cu wiring opposed to the wiring trench.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: June 12, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20120108059
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi Kageyama
  • Patent number: 8164197
    Abstract: A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: April 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 8125050
    Abstract: A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: February 28, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Patent number: 8125084
    Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: February 28, 2012
    Assignee: ROHM Co., Ltd.
    Inventors: Ryosuke Nakagawa, Takahisa Yamaha, Yuichi Nakao, Katsumi Sameshima, Satoshi Kageyama
  • Patent number: 8119519
    Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: February 21, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Patent number: 8110504
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 7, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 8039390
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 18, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Yoshihisa Takada
  • Publication number: 20110215482
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Application
    Filed: May 12, 2011
    Publication date: September 8, 2011
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Patent number: 8008782
    Abstract: A semiconductor device including a first wire made of a material mainly composed of Cu, two second wires made of a material mainly composed of Cu, an interlayer dielectric film formed between the first wire and the two second wires, two vias made of a material mainly composed of Cu and each penetrating through the interlayer dielectric film and connecting the first wire and a respective one of the two second wires, and a dummy via formed between the two second wires. The dummy via is made of a material mainly composed of Cu, has a diameter smaller than a diameter of each of the two vias, and is connected to the first wire while not contributing to electrical connection between the first wire and the two second wires.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: August 30, 2011
    Assignee: ROHM Co., Ltd.
    Inventor: Satoshi Kageyama
  • Patent number: 7974670
    Abstract: A method of processing skin surface observation measuring data which is able to address various sicknesses and reduce an error in sickness detection, and a measuring apparatus requiring no filter. The measuring apparatus an irradiator applying a white light to a biological surface as a sample, a detector detecting the spectra of the white light reflected off a plurality of positions on the biological surface, a plotter plotting the absorbances of the above spectra to a light spectrum multi-dimensional space, an analyzer subjecting data in the spectrum multi-dimension space obtained from the plurality of positions to multivariate analysis to determine the eigenvectors of at least first, second and third principal components, and a display projecting data at respective positions in respective eigenvector directions to display their magnitudes on a two-dimension display screen on a gray scale or in colors corresponding to the magnitudes; and a measuring method by the apparatus.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: July 5, 2011
    Assignee: Waseda University
    Inventors: Takayuki Souta, Katsuo Aizawa, Atsushi Nakamura, Satoshi Kageyama, Shinya Ohtsubo, Fumihiko Ichikawa
  • Publication number: 20110147890
    Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.
    Type: Application
    Filed: March 2, 2011
    Publication date: June 23, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Patent number: 7948094
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: May 24, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Patent number: 7906832
    Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 15, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20110059607
    Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Publication number: 20110045669
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 24, 2011
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 7834459
    Abstract: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: November 16, 2010
    Assignee: Rohm Co., Ltd.
    Inventor: Satoshi Kageyama
  • Publication number: 20100270686
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 28, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Publication number: 20100244264
    Abstract: A semiconductor device including a first wire made of a material mainly composed of Cu, two second wires made of a material mainly composed of Cu, an interlayer dielectric film formed between the first wire and the two second wires, two vias made of a material mainly composed of Cu and each penetrating through the interlayer dielectric film and connecting the first wire and a respective one of the two second wires, and a dummy via formed between the two second wires. The dummy via is made of a material mainly composed of Cu, has a diameter smaller than a diameter of each of the two vias, and is connected to the first wire while not contributing to electrical connection between the first wire and the two second wires.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Patent number: 7777340
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: August 17, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou