Patents by Inventor Satoshi Kageyama
Satoshi Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8198732Abstract: A semiconductor device of the present invention includes an insulating film made of a low dielectric constant material having a smaller specific dielectric constant than SiO2, a wiring trench formed in the insulating film, a first barrier film made of SiO2 or SiCO formed at least on the side surface of the wiring trench, Cu wiring mainly composed of Cu embedded in the wiring trench, and a second barrier film made of a compound containing Si, O and a predetermined metallic element covering the surface of the Cu wiring opposed to the wiring trench.Type: GrantFiled: May 21, 2008Date of Patent: June 12, 2012Assignee: Rohm Co., Ltd.Inventor: Satoshi Kageyama
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Publication number: 20120108059Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Applicant: ROHM CO., LTD.Inventors: Yuichi NAKAO, Satoshi Kageyama
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Patent number: 8164197Abstract: A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface.Type: GrantFiled: August 6, 2008Date of Patent: April 24, 2012Assignee: Rohm Co., Ltd.Inventors: Yuichi Nakao, Satoshi Kageyama
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Patent number: 8125050Abstract: A semiconductor device is described includes a wiring layer, an insulating layer stacked on the wiring layer, a trench formed by digging down the insulating layer from the surface thereof, a film-shaped lower electrode formed along the inner surface of the trench, a capacitor film formed along the surface of the lower electrode, and an upper electrode opposed to the lower electrode with the capacitor film sandwiched therebetween.Type: GrantFiled: May 30, 2008Date of Patent: February 28, 2012Assignee: Rohm Co., Ltd.Inventor: Satoshi Kageyama
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Patent number: 8125084Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portionType: GrantFiled: October 11, 2007Date of Patent: February 28, 2012Assignee: ROHM Co., Ltd.Inventors: Ryosuke Nakagawa, Takahisa Yamaha, Yuichi Nakao, Katsumi Sameshima, Satoshi Kageyama
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Patent number: 8119519Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.Type: GrantFiled: November 12, 2010Date of Patent: February 21, 2012Assignee: Rohm Co., Ltd.Inventor: Satoshi Kageyama
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Patent number: 8110504Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.Type: GrantFiled: August 5, 2009Date of Patent: February 7, 2012Assignee: Rohm Co., Ltd.Inventors: Yuichi Nakao, Satoshi Kageyama
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Patent number: 8039390Abstract: The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.Type: GrantFiled: August 4, 2009Date of Patent: October 18, 2011Assignee: Rohm Co., Ltd.Inventors: Yuichi Nakao, Satoshi Kageyama, Yoshihisa Takada
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Publication number: 20110215482Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.Type: ApplicationFiled: May 12, 2011Publication date: September 8, 2011Inventors: Satoshi Kageyama, Yuichi Nakao
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Patent number: 8008782Abstract: A semiconductor device including a first wire made of a material mainly composed of Cu, two second wires made of a material mainly composed of Cu, an interlayer dielectric film formed between the first wire and the two second wires, two vias made of a material mainly composed of Cu and each penetrating through the interlayer dielectric film and connecting the first wire and a respective one of the two second wires, and a dummy via formed between the two second wires. The dummy via is made of a material mainly composed of Cu, has a diameter smaller than a diameter of each of the two vias, and is connected to the first wire while not contributing to electrical connection between the first wire and the two second wires.Type: GrantFiled: June 7, 2010Date of Patent: August 30, 2011Assignee: ROHM Co., Ltd.Inventor: Satoshi Kageyama
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Patent number: 7974670Abstract: A method of processing skin surface observation measuring data which is able to address various sicknesses and reduce an error in sickness detection, and a measuring apparatus requiring no filter. The measuring apparatus an irradiator applying a white light to a biological surface as a sample, a detector detecting the spectra of the white light reflected off a plurality of positions on the biological surface, a plotter plotting the absorbances of the above spectra to a light spectrum multi-dimensional space, an analyzer subjecting data in the spectrum multi-dimension space obtained from the plurality of positions to multivariate analysis to determine the eigenvectors of at least first, second and third principal components, and a display projecting data at respective positions in respective eigenvector directions to display their magnitudes on a two-dimension display screen on a gray scale or in colors corresponding to the magnitudes; and a measuring method by the apparatus.Type: GrantFiled: February 22, 2005Date of Patent: July 5, 2011Assignee: Waseda UniversityInventors: Takayuki Souta, Katsuo Aizawa, Atsushi Nakamura, Satoshi Kageyama, Shinya Ohtsubo, Fumihiko Ichikawa
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Publication number: 20110147890Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.Type: ApplicationFiled: March 2, 2011Publication date: June 23, 2011Applicant: ROHM CO., LTD.Inventor: Satoshi KAGEYAMA
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Patent number: 7948094Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.Type: GrantFiled: October 22, 2008Date of Patent: May 24, 2011Assignee: Rohm Co., Ltd.Inventors: Satoshi Kageyama, Yuichi Nakao
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Patent number: 7906832Abstract: The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.Type: GrantFiled: October 24, 2008Date of Patent: March 15, 2011Assignee: Rohm Co., Ltd.Inventor: Satoshi Kageyama
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Publication number: 20110059607Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.Type: ApplicationFiled: November 12, 2010Publication date: March 10, 2011Applicant: ROHM CO., LTD.Inventor: Satoshi KAGEYAMA
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Publication number: 20110045669Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.Type: ApplicationFiled: August 5, 2009Publication date: February 24, 2011Applicant: ROHM CO., LTD.Inventors: Yuichi Nakao, Satoshi Kageyama
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Patent number: 7834459Abstract: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.Type: GrantFiled: October 21, 2005Date of Patent: November 16, 2010Assignee: Rohm Co., Ltd.Inventor: Satoshi Kageyama
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Publication number: 20100270686Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.Type: ApplicationFiled: July 2, 2010Publication date: October 28, 2010Applicant: ROHM CO., LTD.Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
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Publication number: 20100244264Abstract: A semiconductor device including a first wire made of a material mainly composed of Cu, two second wires made of a material mainly composed of Cu, an interlayer dielectric film formed between the first wire and the two second wires, two vias made of a material mainly composed of Cu and each penetrating through the interlayer dielectric film and connecting the first wire and a respective one of the two second wires, and a dummy via formed between the two second wires. The dummy via is made of a material mainly composed of Cu, has a diameter smaller than a diameter of each of the two vias, and is connected to the first wire while not contributing to electrical connection between the first wire and the two second wires.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Applicant: ROHM CO., LTD.Inventor: Satoshi Kageyama
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Patent number: 7777340Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.Type: GrantFiled: November 7, 2007Date of Patent: August 17, 2010Assignee: Rohm Co., Ltd.Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou