Patents by Inventor Seung-hun Lee
Seung-hun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942574Abstract: A display device includes a first electrode disposed on a substrate, a first insulating film disposed on the first electrode and having a first opening formed, a second insulating film disposed on the first insulating film and having a second opening, and a contact electrode electrically contacting at least a portion of the first electrode through the first opening and the second opening, wherein a side surface of the first insulating film defines the first opening, and the second insulating film overlaps the side surface of the first insulating film such that the contact electrode and the first insulating film are not in contact with each other.Type: GrantFiled: August 31, 2021Date of Patent: March 26, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seung Jin Chu, Je Min Lee, Hyun Kim, Myeong Hun Song, Jong Chan Lee, Woong Hee Jeong
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Patent number: 11940932Abstract: Provided is an operating method of a storage device. The method includes providing temperature information of each of a plurality of volatile memory devices in the storage device to a host device; and receiving a setting command related to a refresh operation of the plurality of volatile memory devices from the host device, wherein the plurality of volatile memory devices are classified into groups based on temperature information, and wherein the setting command indicates a number of rows of the plurality of volatile memory devices to be refreshed differently for each of the groups based on the temperature information.Type: GrantFiled: June 28, 2021Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo Hwan Oh, Seung-Hun Lee, Jin Hun Jeong, Chang Ho Yun, Kyung-Hee Han
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Publication number: 20240098885Abstract: A communication apparatus is provided to include an apparatus enclosure that includes a substrate seating surface and at least one or more connection grooves formed on the substrate seating surface, a first printed circuit board disposed on the substrate seating surface, a second printed circuit board disposed on the substrate seating surface on one side of the first printed circuit board, and at least one or more connectors disposed within the connection groove and configured to electrically connect the first printed circuit board and the second printed circuit board.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: KMW INC.Inventors: Bae Mook JEONG, Kyo Sung JI, Seong Min AHN, Chi Back RYU, Jae Eun KIM, Seung Min LEE, Ki Hun PARK, Won Jun PARK, Duk Yong KIM
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Publication number: 20240098880Abstract: The present disclosure relates to an electronic device, and more specifically, to an electronic device including a printed circuit board including a heat-generating element arranged on one surface thereof, and a heat transfer coin provided such that one surface of the heat transfer coin comes into contact with a portion of the other surface of the printed circuit board, opposite to the heat-generating element, so as to dissipate heat generated from the heat-generating element. Accordingly, the present disclosure provides an advantage of improving heat dissipation performance without increasing the thickness of the printed circuit board.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: KMW INC.Inventors: Bae Mook JEONG, Kyo Sung JI, Seong Min AHN, Chi Back RYU, Jae Eun KIM, Seung Min LEE, Ki Hun PARK, Won Jun PARK, Jun Woo YANG
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Patent number: 11935943Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.Type: GrantFiled: January 10, 2022Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Kwan Yu, Seung Hun Lee, Yang Xu
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Publication number: 20240076127Abstract: Provided is a ceiling storage system capable of correcting a working position and constantly checking stability of a structure by detecting an amount of change in a facility. According to the ceiling storage system, a transport vehicle moves to an upper portion of a first storage area of a plurality of storage areas in a state of gripping an article, and the transport vehicle measures a first distance value between the transport vehicle and the first storage area using a distance sensor and measures a relative position value between the transport vehicle and the first storage area using a vision sensor, before unloading the article from the first storage area.Type: ApplicationFiled: May 23, 2023Publication date: March 7, 2024Inventors: Sang Kyung LEE, Seung Gyu KANG, Hyun Jae KANG, Young Wook KIM, Sang A BANG, Yong-Jun AHN, Min Kyun LEE, Hyun Woo LEE, Jeong Hun LIM, Jun Hyuk CHANG
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Publication number: 20240063461Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; bus bar assemblies located on both sides of the battery stack, from which the electrode tabs are drawn, to electrically connect the plurality of battery cells to each other through the plurality of electrode tabs; and a sensing module assembly disposed on one side of the battery stack, from which the electrode tab is not drawn out, to electrically connect the bus bar assemblies on both sides of the battery stack.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Seung Hun LEE, Yun Joo NOH, Tae Gu LEE
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Patent number: 11906900Abstract: Proposed is a photoresist composition for a KrF light source, which exhibits a vertical profile compared to conventional KrF positive photoresists by adding a resin capable of increasing transmittance in order to form a semiconductor pattern, particularly a chemically amplified positive photoresist composition for improving a pattern profile, which includes, based on the total weight of the composition, 5 to 60 wt % of a polymer resin, 0.1 to 10 wt % of a transmittance-increasing resin additive represented by Chemical Formula 1, 0.05 to 10 wt % of a photoacid generator, 0.01 to 5 wt % of an acid diffusion inhibitor, and the remainder of a solvent, thus making it possible to provide a composition exhibiting a vertical profile, enhanced sensitivity and a superior processing margin compared to conventional positive photoresists.Type: GrantFiled: May 22, 2019Date of Patent: February 20, 2024Assignee: YOUNG CHANG CHEMICAL CO., LTDInventors: Su Jin Lee, Young Cheol Choi, Seung Hun Lee, Seung Hyun Lee
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Publication number: 20240055482Abstract: A semiconductor device including: first and second cell regions; a substrate including first and second surfaces; first to third active patterns extending in a first horizontal direction in the first cell region, the first to third active patterns spaced apart from each other in a second horizontal direction; a fourth active pattern extending in the first horizontal direction in the second cell region, the fourth active pattern is aligned with the second active pattern in the first horizontal direction; an active cut separating the second and fourth active patterns; a source/drain region on the second active pattern; a buried rail extending in the first horizontal direction on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a source/drain contact penetrating the substrate and second active pattern and connecting the source/drain region to the buried rail.Type: ApplicationFiled: March 31, 2023Publication date: February 15, 2024Inventors: Seok Hyeon YOON, Kyo-Wook LEE, Seung Hun LEE, Seung Han PARK
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Patent number: 11901530Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; and bus bar assemblies located on sides of the battery stack, from which the electrode tabs are drawn out, to electrically connect the plurality of battery cells to each other through a plurality of electrode tabs, wherein each of the bus bar assemblies includes a plurality of openings configured to hold the plurality of electrode tabs, and each of the plurality of openings includes an insertion portion formed by opening one side thereof so that the electrode tab is slidely inserted in a direction perpendicular to a direction in which the electrode tabs are drawn out.Type: GrantFiled: February 7, 2020Date of Patent: February 13, 2024Assignee: SK ON CO., LTD.Inventors: Seung Hun Lee, Tae Gu Lee, Kwan Yong Kim, Kenneth Kim
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Patent number: 11901526Abstract: A battery module includes a cell stack including a plurality of battery cells stacked therein, a bus bar assembly coupled to a side of the cell stack, on which an electrode lead of the battery cell is disposed, and a sensing device coupled to the bus bar assembly and measuring a temperature of the battery cell. The bus bar assembly is coupled to the cell stack in a vertical direction, and the sensing device includes a temperature sensor disposed in close contact with the battery cell, and an elastic bracket pressing the temperature sensor toward the battery cell through elastic force.Type: GrantFiled: December 23, 2021Date of Patent: February 13, 2024Assignee: SK ON CO., LTD.Inventors: Seung Hun Lee, Hyeong Kwan Kang, Kwan Yong Kim, Sang Yeon Kim, Dong Jin Shin, Ung Ho Lee
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Patent number: 11888028Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.Type: GrantFiled: July 12, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinbum Kim, Dahye Kim, Seokhoon Kim, Jaemun Kim, Ilgyou Shin, Haejun Yu, Kyungin Choi, Kihyun Hwang, Sangmoon Lee, Seung Hun Lee, Keun Hwi Cho
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Patent number: 11862679Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.Type: GrantFiled: March 4, 2022Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Hee Choi, Seokhoon Kim, Choeun Lee, Edward Namkyu Cho, Seung Hun Lee
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Publication number: 20230411458Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Inventors: Ilgyou Shin, Minyi Kim, Myung Gil Kang, Jinbum Kim, Seung Hun Lee, Keun Hwi Cho
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Patent number: 11848432Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; bus bar assemblies located on both sides of the battery stack, from which the electrode tabs are drawn, to electrically connect the plurality of battery cells to each other through the plurality of electrode tabs; and a sensing module assembly disposed on one side of the battery stack, from which the electrode tab is not drawn out, to electrically connect the bus bar assemblies on both sides of the battery stack.Type: GrantFiled: February 7, 2020Date of Patent: December 19, 2023Assignee: SK ON CO., LTD.Inventors: Seung Hun Lee, Yun Joo Noh, Tae Gu Lee
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Patent number: 11844238Abstract: A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor.Type: GrantFiled: May 3, 2022Date of Patent: December 12, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jay Bum Kim, Myeong Ho Kim, Kyoung Seok Son, Seung Jun Lee, Seung Hun Lee, Jun Hyung Lim
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Patent number: 11824218Abstract: Provided is a battery module including a pad having characteristics of expanding at a predetermined temperature or higher, thereby blocking a path along which a high-temperature, high-pressure gas discharged from the battery cell in which an event occurs moves, and thus, the gas is prevented from spreading to other battery cells.Type: GrantFiled: July 26, 2021Date of Patent: November 21, 2023Assignee: SK ON CO., LTD.Inventors: Seung Hun Lee, Tae Gu Lee
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Patent number: 11825703Abstract: A display device includes a substrate, a first transistor including a channel on the substrate, a first electrode and a second electrode, and a gate electrode overlapping the channel of the first transistor, a first interlayer insulation layer on the first and second electrodes of the first transistor, a second transistor including a channel disposed on the first interlayer insulation layer, a first electrode and a second electrode of the second transistor, and a gate electrode that overlaps the channel of the second transistor, a first connection electrode disposed on the first interlayer insulation layer, and connected with the first electrode of the first transistor, a gate insulation layer disposed between the first interlayer insulation layer and the first connection electrode, and a second connection electrode that connects the first connection electrode and the first electrode of the second transistor.Type: GrantFiled: April 28, 2021Date of Patent: November 21, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jay Bum Kim, Myeong Ho Kim, Yeon Hong Kim, Kyoung Seok Son, Sun Hee Lee, Seung Jun Lee, Seung Hun Lee, Jun Hyung Lim
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Publication number: 20230352532Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.Type: ApplicationFiled: July 5, 2023Publication date: November 2, 2023Inventors: Cho-eun LEE, Seok-hoon KIM, Sang-gil LEE, Edward CHO, Min-hee CHOI, Seung-hun LEE
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Publication number: 20230350293Abstract: The present invention is for providing an I-line negative photoresist composition exhibiting better process margin than a conventional I-line negative photoresist, has the purpose of alleviating a problem in which the center of a contact hole pattern is dented during pattern formation, and relates to an I-line negative photoresist composition for reducing the height difference, between the center and the edge, formed by the denting of the center and for reducing line edge roughness (LER) during pattern formation in a semiconductor process, the composition comprising: a polymer resin; a compound represented by chemical formula 1; a crosslinking agent; a photoacid generator; an acid diffusion inhibitor; and a solvent.Type: ApplicationFiled: August 26, 2021Publication date: November 2, 2023Inventors: Su Jin LEE, Young Cheol CHOI, Seung Hun LEE, Seung Hyun LEE