Patents by Inventor Seung-hun Lee

Seung-hun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735631
    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cho-eun Lee, Seok-hoon Kim, Sang-gil Lee, Edward Namkyu Cho, Min-hee Choi, Seung-hun Lee
  • Patent number: 11735663
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Patent number: 11728434
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Publication number: 20230255077
    Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Kyoung Seok SON, Myoung Hwa KIM, Jay Bum KIM, Seung Jun LEE, Seung Hun LEE, Jun Hyung LIM
  • Publication number: 20230246029
    Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Inventors: Hyojin KIM, Jihye LEE, Sangmoon LEE, Seung Hun LEE
  • Publication number: 20230226236
    Abstract: The present disclosure relates to a plasma treatment apparatus and a method using the same, and more particularly, to a plasma treatment apparatus for applying, to a target object, such as a biomaterial, characteristics (e.g., removal of organic materials, crosslinking reaction, etching reaction, structural change by surface chemical reaction, sterilization effect, wettability, adhesiveness, bondability, color compatibility, surface reinforcement, modification of surface heat resistance, sterilization, removal of harmful proteins/bacteria, etc.) according to plasma treatment, and a method using the plasma treatment apparatus.
    Type: Application
    Filed: May 28, 2021
    Publication date: July 20, 2023
    Applicant: PLASMAPP CO., LTD.
    Inventors: You Bong LIM, Seung HUn LEE, Jun Young KIM
  • Patent number: 11705520
    Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Dong Woo Kim, Sang Moon Lee, Seung Hun Lee
  • Patent number: 11706954
    Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 18, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myeong Ho Kim, Jay Bum Kim, Kyoung Seok Son, Sun Hee Lee, Seung Jun Lee, Seung Hun Lee, Jun Hyung Lim
  • Publication number: 20230223438
    Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 13, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Haejun YU, Kyungin Choi, Seung Hun Lee
  • Patent number: 11699613
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunguk Jang, Seokhoon Kim, Seung Hun Lee, Yang Xu, Jeongho Yoo, Jongryeol Yoo, Youngdae Cho
  • Publication number: 20230207628
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Inventors: Namkyu Edward CHO, Seung Soo HONG, Geum Jung SEONG, Seung Hun LEE, Jeong Yun LEE
  • Patent number: 11688778
    Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ryong Ha, Dongwoo Kim, Gyeom Kim, Yong Seung Kim, Pankwi Park, Seung Hun Lee
  • Patent number: 11682735
    Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hun Lee, Dong Woo Kim, Dong Chan Suh, Sun Jung Kim
  • Patent number: 11682673
    Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Jinbum Kim, Haejun Yu, Seung Hun Lee
  • Publication number: 20230152621
    Abstract: The present disclosure relates to an anti-glare film including an acrylic substrate and a coating layer located on at least one side of the acrylic substrate, which has a specific rate of change of band area ratio in a graph derived from the result of Raman spectroscopy performed for the coating layer in the thickness direction. It also relates to a polarizing plate, and a display apparatus including the same.
    Type: Application
    Filed: July 20, 2021
    Publication date: May 18, 2023
    Applicant: LG CHEM, LTD.
    Inventors: Seung Hun LEE, Hanna LEE, Jung Hyun SEO, Yeongrae CHANG, Jong Soo DO, Sun Joon OH
  • Patent number: 11653541
    Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: May 16, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyoung Seok Son, Myoung Hwa Kim, Jay Bum Kim, Seung Jun Lee, Seung Hun Lee, Jun Hyung Lim
  • Patent number: 11628206
    Abstract: The present disclosure relates to a method for inhibiting a STAT3 activity comprising administering SSu72 protein.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 18, 2023
    Assignee: CUROGEN TECHNOLOGY CO., LTD.
    Inventors: Mi-La Cho, Sung-Hwan Park, Seung-Ki Kwok, Jong-Young Choi, Seung-Hun Lee, Hyeon-Beom Seo, Young-Mee Moon, Jin-Sil Park, Min-Jung Park, Jin-Kwan Lee, Chang Woo Lee
  • Patent number: 11631670
    Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyojin Kim, Jihye Lee, Sangmoon Lee, Seung Hun Lee
  • Publication number: 20230114353
    Abstract: A rechargeable battery includes an electrode assembly including a first electrode plate, a second electrode plate, and a separator, a case accommodating the electrode assembly and having both ends open, a first cap plate coupled to one end of the case, a second cap plate coupled to the other end of the case, a first cover member disposed to cover the first cap plate and including a first electrode terminal exposed upwardly, and a second cover member disposed to cover the second cap plate and including a second electrode terminal exposed upwardly. A first electrode lead of the electrode assembly passes through the first cap plate to be electrically connected to the first electrode terminal of the first cover member, and a second electrode lead of the electrode assembly passes through the second cap plate to be electrically connected to the second electrode terminal of the second cover member.
    Type: Application
    Filed: July 11, 2022
    Publication date: April 13, 2023
    Inventors: Seung Hun LEE, Suk Chan Kim, Yea Eun Kim, Soo Jy RYU, Se Hwan Oh
  • Patent number: 11624984
    Abstract: A processing solution composition for reducing micro-bridge defects in a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source and a method of forming a pattern using the same are proposed. The processing solution composition includes 0.0001 to 1 wt % of an alkaline material, 0.0001 to 1 wt % of a nonionic surfactant having an HLB (Hydrophilic-Lipophilic Balance) value of 9 to 16, and 98 to 99.9998 wt % of water, reduces the number of micro-bridge defects in a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source, and has a low LWR (Line Width Roughness) value, thus effectively improving the uniformity of the pattern.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 11, 2023
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Seung Hun Lee, Seung Hyun Lee