Abstract: A rechargeable battery includes a case having an internal space having one end thereof open, an electrode assembly disposed in the internal space of the case, and a cap plate coupled to the open case, wherein the electrode assembly has a concave-convex shape in a portion corresponding to the open end when a large surface thereof is viewed.

Abstract: A pixel includes a light emitting element, first through third transistors, sixth through seventh transistors, a ninth transistor, and a capacitor. The first transistor is connected between supply and a second node and controls a driving current supplied to the light emitting element. The second transistor is connected between a third node and a data line. The third transistor is connected between a first node connected to a gate electrode of the first transistor and the second node. The sixth transistor is connected between the supply and a fifth node connected to an electrode of the first transistor. The seventh transistor is connected between the second node and a fourth node connected to an anode of the light emitting element. The ninth transistor is connected between the fifth node and bias. Gate electrodes of the sixth through seventh transistors and the ninth transistor are connected to a same emission line.

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

Abstract: Provided is display device comprising a substrate; a first semiconductor layer disposed on the substrate and having a plurality of transistors; a second semiconductor layer disposed on the first semiconductor layer and having a plurality of transistors; a first data conductive layer disposed on the second semiconductor layer; a first metal layer disposed on the first data conductive layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes a first storage electrode and a first input electrode, the second metal layer includes a second storage electrode and a second input electrode, the first storage electrode and the second storage electrode configure a storage capacitor, and the first input electrode and the second input electrode configure an input capacitor.

Abstract: A pixel includes a light emitting element, first through third transistors, sixth through seventh transistors, a ninth transistor, and a capacitor. The first transistor is connected between supply and a second node and controls a driving current supplied to the light emitting element. The second transistor is connected between a third node and a data line. The third transistor is connected between a first node connected to a gate electrode of the first transistor and the second node. The sixth transistor is connected between the supply and a fifth node connected to an electrode of the first transistor. The seventh transistor is connected between the second node and a fourth node connected to an anode of the light emitting element. The ninth transistor is connected between the fifth node and bias. Gate electrodes of the sixth through seventh transistors and the ninth transistor are connected to a same emission line.

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

Abstract: A display device includes a substrate, a first semiconductor layer on the substrate, a first gate insulating film on the first semiconductor layer, a first conductive layer on the first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode, a second semiconductor layer on the first gate insulating film and at a different layer from the first semiconductor layer, a second gate insulating film on the first conductive layer and the second semiconductor layer, a second conductive layer on the second gate insulating film and including a second gate electrode and a second electrode of the capacitor, a second interlayer insulating film on the second conductive layer, and a third conductive layer on the second interlayer insulating film and including a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode.

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.

Abstract: The present invention relates to a chemically-amplified-type negative photoresist composition, and more particularly to a chemically-amplified-type negative photoresist composition suitable for use in a semiconductor process, which includes a specific organic acid additive, thereby improving a processing margin in a short-wavelength exposure light source compared to conventional negative photoresists.

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

Abstract: The present invention relates to an etching composition for selectively etching a silicon nitride layer. The etching composition includes an inorganic acid, an epoxy-based silicon compound, and water. The etching composition of the present invention selectively removes a silicon nitride layer while minimizing damage to an underlying metal layer and preventing a silicon oxide layer from being etched.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode provided on the channel pattern and extended in a first direction, and an active contact coupled to the source/drain pattern. The active contact includes a buried portion buried in the source/drain pattern and a contact portion on the buried portion. The buried portion includes an expansion portion provided in a lower portion of the source/drain pattern and a vertical extension portion connecting the contact portion to the expansion portion.

Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.

Abstract: Proposed are a processing solution for reducing the incidence of pattern collapse and the number of defects in a photoresist pattern including polyhydroxystyrene using extreme ultraviolet rays as an exposure source, and a method of forming a pattern using the same. The processing solution for reducing the incidence of photoresist pattern collapse and the number of defects includes 0.0001 to 1 wt % of an alkaline material, 0.0001 to 1 wt % of an anionic surfactant, and 98 to 99.9998 wt % of water.

Abstract: Disclosed is a method of forming a fine silicon pattern with a high aspect ratio for fabrication of a semiconductor device. The method includes a cleaning process of removing organic residue or reside originating in fumes using a cleaning solution, thereby enabling formation of a desired pattern while preventing the pattern from being lifted. Thus, the present disclosure enables formation of a fine pattern by using a novel cleaning method.

Abstract: A process liquid composition for moving a lifting defect level of a photoresist pattern having hydrophobicity represented by a contact angle of 75° or larger of a photoresist surface with respect to water in a photoresist patterning process, and a preparation method thereof are proposed. The process liquid composition includes 0.00001% to 0.1% by weight of a fluorine-based surfactant, 0.00001% to 1.0% by weight of a triol derivative, a tetraol derivative, or a mixture thereof, and the remaining proportion of water. The process liquid composition has a surface tension of 45 mN/m or less and a contact angle of 65° or smaller.