Patents by Inventor Shigeru Kusunoki

Shigeru Kusunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100118455
    Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.
    Type: Application
    Filed: May 6, 2009
    Publication date: May 13, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Shigeru KUSUNOKI
  • Publication number: 20100038707
    Abstract: A semiconductor device including: a semiconductor substrate; a first main electrode provided on a first main surface of said semiconductor substrate; a second main electrode provided on a second main surface of said semiconductor substrate, wherein a main current flows in a thickness direction of said semiconductor substrate; a trench that extends from the first main surface of said semiconductor substrate towards the second main surface; a gate insulating film covering an inner surface of said trench; and a gate electrode buried in said trench and surrounded by said gate insulating film.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 18, 2010
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Norifumi TOKUDA, Shigeru KUSUNOKI
  • Patent number: 7635892
    Abstract: A semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface, a semiconductor region provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions provided in the surface of a peripheral region on the second main surface side, and insulating films provided on the side surfaces of the recess to electrically insulate the semiconductor regions.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: December 22, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Patent number: 7629226
    Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: December 8, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Patent number: 7560771
    Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: July 14, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Patent number: 7504707
    Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: March 17, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Publication number: 20090068815
    Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.
    Type: Application
    Filed: November 14, 2008
    Publication date: March 12, 2009
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Publication number: 20080290407
    Abstract: A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.
    Type: Application
    Filed: April 28, 2008
    Publication date: November 27, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shigeru Kusunoki, Koichi Mochizuki, Minoru Kawakami
  • Patent number: 7274953
    Abstract: A dielectric sheet is attached to the inner surface of the portable telephone housing. The dielectric sheet extends in the area between the user's head and a whip antenna of the portable telephone. The real part and the imaginary part of the relative dielectric constant of the dielectric sheet is properly selected such that the dielectric sheet can reduce SAR (Specific Absorption Rate) and improve antenna efficiency.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: September 25, 2007
    Assignee: Kabushiki Kaisha Fine Rubber Kenkyuusho
    Inventors: Kazuhisa Takagi, Yuko Furukawa, Yuji Koyamashita, Shigeru Kusunoki, Sohji Tsuchiya
  • Patent number: 7250345
    Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: July 31, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Publication number: 20070075332
    Abstract: The present invention relates to a semiconductor device; in particular, an object of the invention is to provide a semiconductor device in which a main current flows in a direction of thickness of the semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during photolithography process.
    Type: Application
    Filed: November 20, 2006
    Publication date: April 5, 2007
    Applicant: MITSUBISHI DENKI KABUSHIKI
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Patent number: 7115944
    Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: October 3, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Publication number: 20050280029
    Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).
    Type: Application
    Filed: August 16, 2005
    Publication date: December 22, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Patent number: 6963100
    Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: November 8, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Shigeru Kusunoki
  • Patent number: 6953968
    Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: October 11, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Publication number: 20050212057
    Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.
    Type: Application
    Filed: June 5, 2003
    Publication date: September 29, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Publication number: 20050156283
    Abstract: A semiconductor device in which a main current flows in a direction of thickness of a semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during a photolithography process. The semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface. A semiconductor region is provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions are provided in the surface of a peripheral region on the second main surface side, and insulating films are provided on the side surfaces of the recess to electrically insulate the semiconductor regions.
    Type: Application
    Filed: July 11, 2003
    Publication date: July 21, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norifumi Tokuda, Shigeru Kusunoki
  • Publication number: 20050082607
    Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.
    Type: Application
    Filed: November 1, 2004
    Publication date: April 21, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
  • Publication number: 20050075150
    Abstract: A dielectric sheet is attached to the inner surface of the portable telephone housing. The dielectric sheet extends in the area between the user's head and a whip antenna of the portable telephone. The real part and the imaginary part of the relative dielectric constant of the dielectric sheet is properly selected such that the dielectric sheet can reduce SAR (Specific Absorption Rate) and improve antenna efficiency.
    Type: Application
    Filed: March 5, 2004
    Publication date: April 7, 2005
    Applicant: KABUSHIKI KAISHA FINE RUBBER KENKYUUSHO
    Inventors: Kazuhisa Takagi, Yuko Furukawa, Yuji Koyamashita, Shigeru Kusunoki, Sohji Tsuchiya
  • Publication number: 20050062105
    Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.
    Type: Application
    Filed: November 1, 2004
    Publication date: March 24, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura