Patents by Inventor Shigeru Kusunoki
Shigeru Kusunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100118455Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: ApplicationFiled: May 6, 2009Publication date: May 13, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shigeru KUSUNOKI
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Publication number: 20100038707Abstract: A semiconductor device including: a semiconductor substrate; a first main electrode provided on a first main surface of said semiconductor substrate; a second main electrode provided on a second main surface of said semiconductor substrate, wherein a main current flows in a thickness direction of said semiconductor substrate; a trench that extends from the first main surface of said semiconductor substrate towards the second main surface; a gate insulating film covering an inner surface of said trench; and a gate electrode buried in said trench and surrounded by said gate insulating film.Type: ApplicationFiled: October 16, 2009Publication date: February 18, 2010Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Norifumi TOKUDA, Shigeru KUSUNOKI
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Patent number: 7635892Abstract: A semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface, a semiconductor region provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions provided in the surface of a peripheral region on the second main surface side, and insulating films provided on the side surfaces of the recess to electrically insulate the semiconductor regions.Type: GrantFiled: November 20, 2006Date of Patent: December 22, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norifumi Tokuda, Shigeru Kusunoki
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Patent number: 7629226Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.Type: GrantFiled: November 14, 2008Date of Patent: December 8, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norifumi Tokuda, Shigeru Kusunoki
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Patent number: 7560771Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.Type: GrantFiled: November 1, 2004Date of Patent: July 14, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Patent number: 7504707Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.Type: GrantFiled: June 5, 2003Date of Patent: March 17, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norifumi Tokuda, Shigeru Kusunoki
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Publication number: 20090068815Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.Type: ApplicationFiled: November 14, 2008Publication date: March 12, 2009Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Norifumi Tokuda, Shigeru Kusunoki
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Publication number: 20080290407Abstract: A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.Type: ApplicationFiled: April 28, 2008Publication date: November 27, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shigeru Kusunoki, Koichi Mochizuki, Minoru Kawakami
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Patent number: 7274953Abstract: A dielectric sheet is attached to the inner surface of the portable telephone housing. The dielectric sheet extends in the area between the user's head and a whip antenna of the portable telephone. The real part and the imaginary part of the relative dielectric constant of the dielectric sheet is properly selected such that the dielectric sheet can reduce SAR (Specific Absorption Rate) and improve antenna efficiency.Type: GrantFiled: March 5, 2004Date of Patent: September 25, 2007Assignee: Kabushiki Kaisha Fine Rubber KenkyuushoInventors: Kazuhisa Takagi, Yuko Furukawa, Yuji Koyamashita, Shigeru Kusunoki, Sohji Tsuchiya
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Patent number: 7250345Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.Type: GrantFiled: November 1, 2004Date of Patent: July 31, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Publication number: 20070075332Abstract: The present invention relates to a semiconductor device; in particular, an object of the invention is to provide a semiconductor device in which a main current flows in a direction of thickness of the semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during photolithography process.Type: ApplicationFiled: November 20, 2006Publication date: April 5, 2007Applicant: MITSUBISHI DENKI KABUSHIKIInventors: Norifumi Tokuda, Shigeru Kusunoki
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Patent number: 7115944Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).Type: GrantFiled: August 16, 2005Date of Patent: October 3, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Publication number: 20050280029Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).Type: ApplicationFiled: August 16, 2005Publication date: December 22, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Patent number: 6963100Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.Type: GrantFiled: September 3, 2002Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventor: Shigeru Kusunoki
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Patent number: 6953968Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).Type: GrantFiled: January 19, 2001Date of Patent: October 11, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Publication number: 20050212057Abstract: A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.Type: ApplicationFiled: June 5, 2003Publication date: September 29, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Norifumi Tokuda, Shigeru Kusunoki
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Publication number: 20050156283Abstract: A semiconductor device in which a main current flows in a direction of thickness of a semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during a photolithography process. The semiconductor device has a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a recess defined in the second main surface by side surfaces and a bottom surface. A semiconductor region is provided in the bottom surface of the recess of the semiconductor substrate, semiconductor regions are provided in the surface of a peripheral region on the second main surface side, and insulating films are provided on the side surfaces of the recess to electrically insulate the semiconductor regions.Type: ApplicationFiled: July 11, 2003Publication date: July 21, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Norifumi Tokuda, Shigeru Kusunoki
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Publication number: 20050082607Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.Type: ApplicationFiled: November 1, 2004Publication date: April 21, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura
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Publication number: 20050075150Abstract: A dielectric sheet is attached to the inner surface of the portable telephone housing. The dielectric sheet extends in the area between the user's head and a whip antenna of the portable telephone. The real part and the imaginary part of the relative dielectric constant of the dielectric sheet is properly selected such that the dielectric sheet can reduce SAR (Specific Absorption Rate) and improve antenna efficiency.Type: ApplicationFiled: March 5, 2004Publication date: April 7, 2005Applicant: KABUSHIKI KAISHA FINE RUBBER KENKYUUSHOInventors: Kazuhisa Takagi, Yuko Furukawa, Yuji Koyamashita, Shigeru Kusunoki, Sohji Tsuchiya
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Publication number: 20050062105Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.Type: ApplicationFiled: November 1, 2004Publication date: March 24, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Katsumi Nakamura, Shigeru Kusunoki, Hideki Nakamura