Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.

Abstract: A field effect transistor according to the present invention uses a silicon monocrystalline substrate. At least two independent thin amorphous silicon layers are formed in a position for preventing movement of majority carriers in a channel region in the surface of the silicon substrate. Each amorphous silicon layer is between monocrystalline silicon layers. A gate electrode is formed on the surface of the channel region through a gate insulating layer. Thin potential barriers and a potential well are formed in the channel region by at least two amorphous silicon layers. Sharp potential barriers are formed by forming thin amorphous silicon layers, and a field effect transistor utilizing the resonant-tunneling effect with high tunneling efficiency is implemented.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: A multi-layer type semiconductor device is disclosed, in which a plurality of semiconductor layers are formed in vertically opposite directions. The multi-layer type semiconductor device is obtained by forming a first semiconductor layer, an insulating layer and a second semiconductor layer in the mentioned order on a main surface of a first substrate, forming a semiconductor device by using the second semiconductor layer as a base, with an exposed surface thereof directed upward, forming an insulating film on the semiconductor device, attaching a second substrate to the insulating film, thinning the first substrate to expose the first semiconductor layer, and forming a further semiconductor device by using the first semiconductor layer as a base, with an exposed surface of the first semiconductor layer directed upward.

Abstract: A multi-layer type semiconductor device is disclosed, in which a plurality of semiconductor layers are formed in vertically opposite directions. The multi-layer type semiconductor device is obtained by forming a first semiconductor layer, an insulating layer and a second semiconductor layer in the mentioned order on a main surface of a first substrate, forming a semiconductor device by using the second semiconductor layer as a base, with an exposed surface thereof directed upward, forming an insulating film on the semiconductor device, attaching a second substrate to the insulating film, thinning the first substrate to expose the first semiconductor layer, and forming a further semiconductor device by using the first semiconductor layer as a base, with an exposed surface of the first semiconductor layer directed upward.

Abstract: An electric cooking apparatus includes a single power converter section for converting power supplied from an external AC power source. A heating-energy radiator section receives the converted power from the power converter section and radiates heating energy to a heating chamber. A battery is also provided for supplying power to the power converter section such that a sum of the power from the external AC power source and the battery is converted by the power converting section when an instantaneous voltage of the external AC power source is smaller than a predetermined voltage level, which predetermined voltage level is smaller than a maximum instantaneous voltage of the external AC power source.

Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10 .sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: An apparatus for regenerating a filter provided to scavenge particulate which is included in exhaust gas discharged from an internal combustion engine. The apparatus includes a heating room accommodating the filter, a heat-combusting device for heat-combusting the particulate scavenged by the filter, a microwave generating device for generating a microwave to be supplied to the heating room, a slit provided in a wall of the heating room, a microwave detecting device for detecting the energy level of the microwave coupled through the slit, and a control section for controlling the heat-combusting device.

Abstract: A multi-layer type semiconductor device is disclosed, in which a plurality of semiconductor layers are formed in vertically opposite directions. The multi-layer type semiconductor device is obtained by forming a first semiconductor layer, an insulating layer and a second semiconductor layer in the mentioned order on a main surface of a first substrate, forming a semiconductor device by using the second semiconductor layer as a base, with an exposed surface thereof directed upward, forming an insulating film on the semiconductor device, attaching a second substrate to the insulating film, thinning the first substrate to expose the first semiconductor layer, and forming a further semiconductor device by using the first semiconductor layer as a base, with an exposed surface of the first semiconductor layer directed upward.

Abstract: A high-frequency heating apparatus includes: a high-frequency oscillator for generating high-frequency electromagnetic waves using electrical power supplied from a power source circuit; a heating chamber into which the high-frequency electromagnetic waves are supplied by the high-frequency oscillator; a receiving antenna which is provided outside the heating chamber and adjacent to an opening of the heating chamber; a dielectric plate for covering the opening, which is provided between the heating chamber and the antenna; and a control circuit which receives an output from the antenna via a detector so as to output a control signal to the power source circuit.

Abstract: A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer.

Abstract: A wafer structure for forming a semiconductor single crystal film comprises a semiconductor single crystal substrate, a plurality of recesses formed in a grooved shape to one main surface of the semiconductor single crystal substrate, insulation material embedded to the inside of these recesses, an insulation layer deposited over the insulation material and the semiconductor single crystal substrate and integrated with the insulation material and a polycrystalline or amorphous semiconductor layer to be recrystallized disposed over the insulation layer.A wafer structure with no or less grain boundaries can be obtained. Further, polycrystalline or amorphous semiconductor layer can be prevented from peeling off the substrate by the additional layering of a protecting insulation layer.

Abstract: A high-frequency heating apparatus comprises an inverter including a semiconductor switch and a resonance capacitor, a boosting transformer for a supplying high-voltage power and heater to a magnetron an inductance device inserted in the heater circuit of the magnetron, and an inverter control unit for controlling the semiconductor switch. The inverter control unit is controlled by a start control at the start time of the inverter so that the conduction time of the semiconductor switch becomes shorter than that under a normal operating condition and the non-conduction time thereof becomes longer than that under a normal operating condition and so that the switching period of the semiconductor switch becomes substantially an integral multiple of a resonance period of the resonance circuit formed by the resonance capacitor, whereby the operating frequency of the inverter at the time of starting thereof becomes substantially equal to its normal operating frequency.

Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.

Abstract: A SOI-MOSFET formed on a thin semiconductor layer (3) having a thickness not more than 1500.ANG. includes a charge carrier absorbing region (9a, 9b, 9c) contacting with at least a portion of the bottom of a channel region (6) of a first conductivity type and with at least a portion of the bottom of a source region (7, 7a) of a second conductivity type. The carrier absorbing region (9a, 9b, 9c) absorbs excess carriers of the first conductivity type contained in the channel region (6).

Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10.sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.

Abstract: A field effect transistor is formed as a first semiconductor element on a main surface of a first semiconductor layer (1). An interlayer insulating film (10) constituted by a first insulating layer (101) and a second insulating layer (102) is formed on the first semiconductor element. The first insulating layer (101) is formed of a BPSG film having a glass transition point no higher than 750.degree. C. The second insulating layer (102) is formed of a silicon oxide film having a glass transition point higher than 750.degree. C. and a thickness no less than 2000 .ANG. and no more than 1 .mu.m formed on the first insulating layer (101). A second semiconductor layer (11) is formed on the second insulating layer (102) of the interlayer insulating film (10). The second semiconductor layer (11) is formed to be an island, with the peripheral portions isolated. A field effect transistor as a second semiconductor element is formed in the second semiconductor layer (11).

Abstract: In an apparatus which produces high frequency electromagnetic waves, a choke portion is provided in a leakage transmission path, which choke portion has a groove wall corresponding to a grounded conductor, a number of strip conductors arranged with a line width a and a pitch p, and a groove bottom, so as to minimize leakage propagation in the longitudinal direction of the groove. Further, this choke portion is designed so that the characteristic impedance of its portion is changed in a region shorter than .lambda./4 of the frequency to be used. As a result, the depth and .[.width.]. .Iadd.clearance .Iaddend.of the groove can .[.also.]. .Iadd.both .Iaddend.be made less than .lambda./4.