Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 &mgr;m and no greater than 250 &mgr;m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 &mgr;m and no greater than 250 &mgr;m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n− silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n− silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n− silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n− silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n− silicon substrate (1).

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract: A semiconductor device including a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween; a second gate insulation film including a ferroelectric and formed on a second plane of the first gate electrode which is provided opposite to the first plane; and a second gate electrode provided opposite to the first gate electrode through the second gate insulation film, wherein the second gate electrode has a second semiconductor region provided in contact with the second gate insulation film, a depletion layer is generated in the second semiconductor region when a first voltage is applied, and a width of the depletion layer is smaller than in the case where the first voltage is applied to the depletion layer disappears when a second voltage is applied, and the second voltage causes more current to flow through the channel than the first voltage.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: An emitter-side structure (2) is formed at an upper main surface of a silicon substrate (1), and an n-type buffer layer (3) is formed at a lower main surface thereof. A p-type collector layer (4) is formed in a main surface of the n-type buffer layer (3), and an n-type cathode region (6) is selectively formed in spaced apart relation with the p-type collector layer (4). A collector electrode (5p) of metal is formed in contact with the p-type collector layer (4), and a cathode electrode (5n) of metal is formed in contact with the n-type cathode region (6) and part of the n-type buffer layer (3). A diode (13) serving as a current suppressing device is connected between the cathode electrode (5n) and a collector terminal (c). A power semiconductor device including an IGBT and a free wheeling diode is reduced in size, and prevents device breakdown due to current concentration during the operation of the free wheeling diode incorporated in the IGBT.

Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Abstract: Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate insulation film 4 in an OFF state, and the depletion layer disappears or a width thereof is reduced in an ON state.

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: A method of simulating hot carrier deterioration of a P-MOS transistor uses the following formulas (A1), (A2), (A3) and (A4) or the following formulas (A1), (A5), (A3) and (A4) (A2), and coefficients A, n, B and m are determined by a preliminary measuring experiment, whereby a transistor lifetime r can be estimated:Vth=Vfb+.sigma..cndot.Vd (A1).DELTA.Vth=.DELTA.Vfb (A2)(.DELTA.Vfb).sub.f =A.cndot..sigma..sup.n (A3).tau.=B.cndot.(Ig/W).sup.-m (A4).DELTA.Vth=.DELTA.Vfb+.DELTA..sigma..cndot.

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.

Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising stripes of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection fil