Patents by Inventor Shinichi Hoshi

Shinichi Hoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090242937
    Abstract: A semiconductor device has source and drain electrodes formed on a substrate, a gate insulation film formed on the substrate between the source and drain electrodes, and a gate electrode formed on the gate insulation film. These elements are all covered by a dielectric sub-insulation film. An opening is formed in the sub-insulation film, partially exposing the gate electrode. A field plate extends from the top of the gate electrode down one side of the gate electrode as far as the sub-insulation film covering the gate insulation film, filling the opening. The thickness of the sub-insulation film can be selected to optimize the separation between the field plate and the substrate for the purpose of reducing current collapse by reducing electric field concentration at the edge of the gate electrode.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 1, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Toshiharu Marui, Fumihiko Toda, Shinichi Hoshi
  • Publication number: 20090212324
    Abstract: An aspect of the invention provides a heterojunction field effect transistor that comprises: a base; a first GaN channel layer formed on the base; an AlN electron supply layer formed on the first GaN layer, and a second GaN cap layer formed on the AlN layer.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 27, 2009
    Applicant: OKI Electric Industry Co., Ltd.
    Inventors: Isao TAMAI, Fumihiko Toda, Shinichi Hoshi
  • Publication number: 20090045439
    Abstract: A heterojunction field effect transistor includes a laminated body. The laminated body includes a channel layer of GaN, an electron supply layer of AlN or AlxGa1-xN (0.6?x<1) formed on the channel layer, and a cap layer of GaN formed on the electron supply layer.
    Type: Application
    Filed: July 15, 2008
    Publication date: February 19, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinichi Hoshi, Isao Tamai, Fumihiko Toda
  • Publication number: 20090001381
    Abstract: A semiconductor device includes a substrate, laminated layers provided on the substrate. The laminated layers include an AlGaN barrier layer as an uppermost layer. A gate electrode is provided in a channel region of the laminated layers. A source electrode and a drain electrode are provided so as to face each other via the channel region interposed therebetween. A silicon nitride film is formed to cover an exposed surface of the laminated layers exposed via the gate electrode, the source electrode and the drain electrode. The silicon nitride film has characteristics that an etching rate thereof is in a range from 1 nm per/min to 2 nm/min for an etchant in which hydrofluoric acid having a concentration of 50 weight percent and ammonium fluoride having a concentration of 40 weight percent are mixed at a mixing ratio of 1:9.
    Type: Application
    Filed: May 28, 2008
    Publication date: January 1, 2009
    Applicant: OKI ELECTRIC INDUSTRY., LTD.
    Inventors: Toshiharu Marui, Hideyuki Okita, Shinichi Hoshi, Fumihiko Toda
  • Publication number: 20080283844
    Abstract: An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.
    Type: Application
    Filed: May 8, 2008
    Publication date: November 20, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinichi Hoshi, Masanori Itoh, Hideyuki Okita, Toshiharu Marui
  • Publication number: 20080272443
    Abstract: A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 6, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinichi Hoshi, Masanori Itoh, Hideyuki Okita, Toshiharu Marui
  • Publication number: 20080182069
    Abstract: This invention relates to a luminescent sheet obtained by allowing a sheet capable of causing luminescence to be subjected to perforation processing; and a method of producing the luminescent sheet, wherein the luminescent sheet is subjected to perforation processing involving drilling, heated needle, punching, flat die cutting, rotary die cutting, laser processing, or the like. According to the present invention, a low-power-consuming luminescent sheet obtained in a more convenient manner is provided.
    Type: Application
    Filed: October 25, 2007
    Publication date: July 31, 2008
    Applicant: LINTEC CORPORATION
    Inventors: Shinichi Hoshi, Shigeto Okuji, Masahiko Sekiya
  • Publication number: 20080118704
    Abstract: This invention relates to a luminescent sheet having see-through property, through which see-through holes are formed and which comprises a means of causing luminescence; a method of producing the luminescent sheet, comprising carrying out perforation processing on a sheet body comprising a means of causing luminescence so as to impart see-through property to such sheet body; and a method of producing the luminescent sheet, comprising carrying out perforation processing on a sheet body so as to impart see-through property to such sheet body and then applying a means of causing luminescence to the sheet body. According to this invention, a luminescent decorative material having see-through property, which is visible even at night and of which different decorative properties are visible in the daytime or under lighting due to the presence or absence of luminescence, is provided.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 22, 2008
    Applicant: LINTEC CORPORATION
    Inventors: Shigeto OKUJI, Masahiko Sekiya, Shinichi Hoshi
  • Publication number: 20080090030
    Abstract: According to this invention, a luminescent decorative material, which is visible even at night, of which different decorative properties are obtained in the daytime or under lighting due to the presence or absence of luminescence is provided. A luminescent sheet (plane sheet) having see-through property and comprising a transparent part, through which it is possible to see the area behind the plane sheet, and a luminescent part is provided.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: LINTEC CORPORATION
    Inventors: Shigeto OKUJI, Masahiko Sekiya, Shinichi Hoshi
  • Publication number: 20080023727
    Abstract: Deterioration of the high frequency characteristics of a field effect transistor is prevented, and the on- and off-gate leakage currents are reduced. A field effect transistor comprises the fourth electrode 126 between the gate electrode 122 and the drain electrode 118. The fourth electrode is formed to satisfy the relationship of 0.25=(FP2?D)/Lgd=0.5, where Lgd represents a distance between the gate and drain electrodes and FP2?D does the distance between the drain and fourth electrodes.
    Type: Application
    Filed: July 24, 2007
    Publication date: January 31, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinichi Hoshi, Masanori Itoh
  • Publication number: 20070132037
    Abstract: The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 14, 2007
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Shinichi Hoshi, Masanori Itoh
  • Publication number: 20050161704
    Abstract: The semiconductor device (10) comprises a semiinsulating substrate (12), a layered structure (20) of compound semiconductor which is a mesa structure (18) and contains an active channel layer (14), a first and a second metal main electrodes (22a, 22b) which are provided on the layered structure (20), a first and a second ion implantation regions (40a, 40b) which are provided at the depth level below the active channel layer, and a metal control electrode (26) which is provided along the channel width direction from the first ion implantation region to the second ion implantation region, crossing over the upper side of the active channel layer.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 28, 2005
    Inventors: Shinichi Hoshi, Tomoyuki Ohshima, Hironobu Moriguchi
  • Publication number: 20030089602
    Abstract: A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 15, 2003
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Shinichi Hoshi
  • Patent number: 6537865
    Abstract: A semiconductor device fabrication process includes forming a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure having a lower portion that penetrates through the cap layer and reaches the Schottky layer, and having an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: March 25, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Patent number: 6383853
    Abstract: A method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Aluminum is vapor deposited on a spacer film from an oblique direction to form a metal film etching guard. Specifically, Al is vapor deposited from a direction inclined from the direction of the normal line of the surface of the spacer film by 85° (angle of vapor deposition). For example, when the depth of a recess is 0.10 &mgr;m and the opening width is 0.4 &mgr;m, Al is not vapor deposited on the bottom surface of the recess. After performing anisotropic etching on the spacer film by using the metal film etching guard as a mask, the metal film etching guard is removed. A gate electrode is formed in the recess.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: May 7, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shinichi Hoshi
  • Publication number: 20020024057
    Abstract: A semiconductor device according to the invention comprises a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure, having an under structure penetrating through the cap layer and reaching the Schottky layer, and an upper structure larger than the under structure in a cross-sectional area and overlying the cap layer. With such a construction as described, surface defect is unlikely to occur, and therefore, a highly reliable semiconductor device can be fabricated.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 28, 2002
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Publication number: 20020004274
    Abstract: Disclosed is a method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Al is vapor deposited on a spacer film 5 from an oblique direction to form a metal film 6 for etching guard. Specifically, Al is vapor deposited from a direction inclined from the direction (n) of the normal line of the surface of the SiO2 spacer film 5 by 85° (angle of vapor deposition) (direction of arrows in the drawing, which is inclined from the surface of the spacer film by 5). For example, when the depth of a recess is 0.10 &mgr;m and the opening width is 0.4 &mgr;m, Al is not vapor deposited on the bottom surface of the recess R. After performing anisotropic etching on the spacer film 5 by using the metal film 6 for etching guard as a mask, the metal film 6 for etching guard is removed. A gate electrode is formed in the recess.
    Type: Application
    Filed: March 6, 2001
    Publication date: January 10, 2002
    Inventor: Shinichi Hoshi
  • Publication number: 20010027020
    Abstract: A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
    Type: Application
    Filed: January 23, 2001
    Publication date: October 4, 2001
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Shinichi Hoshi
  • Patent number: 6294801
    Abstract: A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 25, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuyuki Inokuchi, Seiichi Takahashi, Shinichi Hoshi, Tadashi Saito, Nobusuke Yamamoto, Yuko Itoh, Nobumasa Higemoto
  • Patent number: 6207499
    Abstract: A method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 27, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shinichi Hoshi