Patents by Inventor Shoji Yoshida

Shoji Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9508554
    Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuharu Yamabe, Shinichiro Abe, Shoji Yoshida, Hideaki Yamakoshi, Toshio Kudo, Seiji Muranaka, Fukuo Owada, Daisuke Okada
  • Patent number: 9485045
    Abstract: Communication control equipment is connected to a plurality of communication control equipment via a network and is configured to be time-synchronized with the plurality of communication control equipment by using a time synchronization procedure using a communication including at least request packets and acknowledgement packets. The communication control equipment includes a receiving-interval measurement section configured to measure a receiving interval of request packets from the plurality of communication control equipment; and a queuing-occurrence determination section configured to detect conflict of the request packets from any of the plurality of communication control equipment on a basis of the receiving interval of the request packets measured by the receiving-interval measurement section.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 1, 2016
    Assignee: HITACHI, LTD.
    Inventors: Tatsuya Maruyama, Tsutomu Yamada, Mitsuyasu Kido, Shoji Yoshida
  • Publication number: 20160190145
    Abstract: A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 30, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Keiichi MAEKAWA, Shoji YOSHIDA, Takashi TAKEUCHI, Hiroshi YANAGITA
  • Publication number: 20160099358
    Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.
    Type: Application
    Filed: September 30, 2015
    Publication date: April 7, 2016
    Inventors: Yoshiyuki KAWASHIMA, Shoji YOSHIDA
  • Publication number: 20160093499
    Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 31, 2016
    Inventors: Kazuharu YAMABE, Shinichiro ABE, Shoji YOSHIDA, Hideaki YAMAKOSHI, Toshio KUDO, Seiji MURANAKA, Fukuo OWADA, Daisuke OKADA
  • Patent number: 9118173
    Abstract: Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Chikashi Komatsu, Mitsuyasu Kido, Shoji Yoshida, Kazuhisa Takami
  • Publication number: 20140146430
    Abstract: Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof.
    Type: Application
    Filed: February 3, 2010
    Publication date: May 29, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Chikashi Komatsu, Mitsuyasu Kido, Shoji Yoshida, Kazuhisa Takami
  • Publication number: 20140098706
    Abstract: Communication control equipment is connected to a plurality of communication control equipment via a network and is configured to be time-synchronized with the plurality of communication control equipment by using a time synchronization procedure using a communication including at least request packets and acknowledgement packets. The communication control equipment includes a receiving-interval measurement section configured to measure a receiving interval of request packets from the plurality of communication control equipment; and a queuing-occurrence determination section configured to detect conflict of the request packets from any of the plurality of communication control equipment on a basis of the receiving interval of the request packets measured by the receiving-interval measurement section.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 10, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Tatsuya MARUYAMA, Tsutomu YAMADA, Mitsuyasu KIDO, Shoji YOSHIDA
  • Patent number: 8497445
    Abstract: A vacuum valve includes a hermetically sealed vessel having an insulative cylinder, an end plate at a movable electrode end, and an end plate at a fixed electrode end. The vessel accommodates a movable contact and an opposed fixed contact. The movable contact is supported through a bellows allowing the contacts to open and close while maintaining an air-tight (hermetic) seal. The bellows used in at least one embodiment is a seam type bellows without metal plating. Nickel plating layers are formed on the end plate at movable contact end and on a cover, which are joined to the bellows. The ends of the bellows are soldered with the end plate and the cover using a silver solder at the solder joints.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: July 30, 2013
    Assignee: Fuji Electric FA Components & Systems Co., Ltd.
    Inventors: Shoji Yoshida, Nobuyuki Odaka, Masayuki Furusawa
  • Patent number: 8330998
    Abstract: A scanner device includes a scanner body enclosed by a housing and an external cover covering an outer side of the housing. The external cover is comprised of a plurality of external members. By spacing the adjacent external members apart from each other at the side edge parts of the housing, recesses are formed between the adjacent external members so as to constitute parts of the external design of the scanner body. Preferably, the side edge parts of the housing are exposed between the adjacent external members at the side edge parts of the housing, and information providing devices providing information on the scanner device are provided at the side edge parts of the housing exposed between the adjacent external members.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: December 11, 2012
    Assignee: PFU Limited
    Inventors: Shoji Yoshida, Hideaki Shibata, Yasuhiro Matsuda, Masaaki Yamashita
  • Patent number: 8169669
    Abstract: A scanner device includes a scanner body formed with a document insertion opening and a document ejection opening and is configured so that a document taken in from the document insertion opening is read and then ejected from the document ejection opening. The scanner device further includes an upper surface cover covering the upper surface of the scanner body and a front surface cover covering the front surface of the scanner body. The front cover is connected at a lower end side thereof to the lower front part of the scanner body and connected at an upper end side thereof to pivotably connected to the front end side of the upper surface cover. By opening the front surface cover from the front surface of the scanner body, the upper surface cover and front surface cover form a document ejection tray.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: May 1, 2012
    Assignee: PFU Limited
    Inventors: Shoji Yoshida, Hideaki Shibata, Yasuhiro Matsuda, Masaaki Yamashita
  • Patent number: 8035169
    Abstract: A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Ishida, Atsushi Maeda, Minoru Abiko, Takehiko Kijima, Takashi Takeuchi, Shoji Yoshida, Natsuo Yamaguchi, Yasuhiro Kimura, Tetsuya Uchida, Norio Ishitsuka
  • Patent number: 7938395
    Abstract: A sheet feeding device includes a driven roller that rotates in response to movement of a sheet, and a rotary encoder that detects a moving distance of the sheet based on rotation of the driven roller. The driven roller and the rotary encoder are connected by a gear unit having backlash. When the sheet moves in a reverse direction and thereby the driven roller rotates in reverse, the rotary encoder does not detect the moving distance of the sheet.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: May 10, 2011
    Assignee: PFU Limited
    Inventors: Shoji Yoshida, Takeshi Kimura
  • Patent number: 7750427
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Publication number: 20100140711
    Abstract: Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element before an ion implantation of impurities to a silicon substrate. In this manner, by separately implanting dislocation-suppressing elements suitable for each of the P-well layer and the N-well layer as well as suppressing the generation of dislocation, increase of diffusion resistance can be suppressed, yield can be improved, and the reliability of devices can be increased.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 10, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Norio ISHITSUKA, Hiroyuki OHTA, Yasuhiro KIMURA, Natsuo YAMAGUCHI, Takashi TAKEUCHI, Shoji YOSHIDA
  • Publication number: 20100060948
    Abstract: A scanner device includes a scanner body enclosed by a housing and an external cover covering an outer side of the housing. The external cover is comprised of a plurality of external members. By spacing the adjacent external members apart from each other at the side edge parts of the housing, recesses are formed between the adjacent external members so as to constitute parts of the external design of the scanner body. Preferably, the side edge parts of the housing are exposed between the adjacent external members at the side edge parts of the housing, and information providing devices providing information on the scanner device are provided at the side edge parts of the housing exposed between the adjacent external members.
    Type: Application
    Filed: August 14, 2009
    Publication date: March 11, 2010
    Applicant: PFU LIMITED
    Inventors: Shoji YOSHIDA, Hideaki Shibata, Yasuhiro Matsuda, Masaaki Yamashita
  • Publication number: 20100053701
    Abstract: A scanner device includes a scanner body formed with a document insertion opening and a document ejection opening and is configured so that an document taken in from the document insertion opening is read and then ejected from the document ejection opening. The scanner device further includes an upper surface cover covering the upper surface of the scanner body and a front surface cover covering the front surface of the scanner body. The front cover is connected at a lower end side thereof to the lower front part of the scanner body and connected at an upper end side thereof to pivotably connected to the front end side of the upper surface cover. By opening the front surface cover from the front surface of the scanner body, the upper surface cover and front surface cover form a document ejection tray.
    Type: Application
    Filed: August 6, 2009
    Publication date: March 4, 2010
    Applicant: PFU LIMITED
    Inventors: Shoji YOSHIDA, Hideaki Shibata, Yasuhiro Matsuda, Masaaki Yamashita
  • Publication number: 20100006755
    Abstract: An object of the present invention is to provide a charged particle beam apparatus and an alignment method of the charged particle beam apparatus, which make it possible to align an optical axis of a charged particle beam easily even when a state of the charged particle beam changes. The present invention comprises calculation means for calculating a deflection amount of an alignment deflector which performs an axis alignment for an objective lens, a plurality of calculation methods for calculating the deflection amount is memorized in the calculation means, and a selection means for selecting at least one of the calculation methods is provided.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 14, 2010
    Inventors: Mitsugo Sato, Tadashi Otaka, Makoto Ezumi, Atsushi Takane, Shoji Yoshida, Satoru Yamaguchi, Yasuhiko Ozawa
  • Patent number: 7642514
    Abstract: It is an object of the present invention to obtain an image which is focused on all portions of a sample and to provide a charged particle beam apparatus capable of obtaining a two-dimensional image which has no blurred part over an entire sample. In order to achieve the above object, the present invention comprises means for changing a focus condition of a charged particle beam emitted from a charged particle source, a charged particle detector for detecting charged particles irradiated from a surface portion of said sample in response to the emitted charged particle beam, and means for composing a two-dimensional image of the surface portion of the sample based on signals on which said charged particle beam is focused, said signals being among signals output from the charged particle detector.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 5, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Takane, Haruo Yoda, Hideo Todokoro, Fumio Mizuno, Shoji Yoshida, Mitsuji Ikeda, Mitsugu Sato, Makoto Ezumi
  • Patent number: 7605381
    Abstract: An object of the present invention is to provide a charged particle beam apparatus and an alignment method of the charged particle beam apparatus, which make it possible to align an optical axis of a charged particle beam easily even when a state of the charged particle beam changes. The present invention comprises calculation means for calculating a deflection amount of an alignment deflector which performs an axis alignment for an objective lens, a plurality of calculation methods for calculating the deflection amount is memorized in the calculation means, and a selection means for selecting at least one of the calculation methods is provided.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: October 20, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Mitsugu Sato, Tadashi Otaka, Makoto Ezumi, Atsushi Takane, Shoji Yoshida, Satoru Yamaguchi, Yasuhiko Ozawa